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2009 IEDM Short Courses
Low Power / Low Energy Circuits: From Device to System Aspects
Sunday, December 6, 9:00 a.m. - 5:30 p.m.
Key Ballrooms 7, 9 and 10
Course Organizer: Reinout Woltjer, NXP Semiconductors
Continuous CMOS scaling through a number of decades has opened the way to a huge amount of various applications. Communication, computer, consumer, automotive, industrial, security, medical and many other products benefit from a continuously increasing functionality and data and signal processing capability per chip. On the other hand, this trend has also driven an increasing need to reduce and manage power consumption of related chips – in other words to minimize used energy per functional operation. This of course applies to all mobile and many medical applications where battery lifetime is a crucial criterion for the entire system performance. Moreover, it applies as well to highly integrated logic (and memory) chips with highest data rates and processing speeds where cooling has become an increasingly growing challenge.
In more detail we have to distinguish between various aspects of power consumption such as active power, leakage and standby power. Power consumption on chip level and on system level (on- and off-chip busses, package, parasitics, temperature, …) are of different importance in the different application field of related chips. A number of physical limits and boundary conditions exist on the electron device level such as kT/q in standard charge based devices, voltage margins to compensate for variability effects and many more. It is clear that a thorough understanding and optimization on device level must meet circuit, system, and application specific considerations to face this challenge.
Moreover, not only practical and technical aspects require striving for low power, also economic, environmental, and political considerations have begun to play an important role. Electronic tools and devices are known to consume an important and increasing amount of the entire energy produced by the industrial world. Hence, regulations have been or will be introduced and programs are on their way to make electronics “greener” in the context of decreasing power hunger.
This short course reviews the requirements, current status and state-of-the-art approaches, challenges and future options of Low Power and Low Energy Circuits. We approach it from a comprehensive standpoint considering devices and device options, circuit design strategies and related aspects of circuit-device-interaction, packaging and system-level issues, and emerging and disruptive approaches.
We start with a short introduction summarizing basic issues and giving a brief overview about the entire complexity behind the easily said requirement “Low Power / Low Energy”. The first lecture addresses this topic from a device level related view applied to standard logic and mixed-signal processes. Process options from bulk technologies to SOI and SoN and related device approaches are discussed in terms of technical performance but also in terms of processing effort and costs. The second lecture provides a comprehensive discussion of power-aware design strategies and makes the link between technology and design solutions concerning the different power contributions. After that the various memory technologies are highlighted. As these have to fulfill different technical boundary conditions as compared to the logic world also technical answers and challenges are different. In the fourth lecture, the impact of the backend-of-line on power issues is addressed and opportunities in 3D integration as a remarkable amount of power is also used to drive on- and off-chip interconnects. Finally, in the fifths lecture, an overview about emerging and disruptive device concepts is given. Today’s status, their potential, and technical challenges are discussed considering devices such as nanotubes, iMOS and tunnel transistors, Carbon and Graphene devices, and nano relays.
Introduction
Reinout Woltjer, NXP Semiconductors
Low Power Logic and Mixed-Signal Technologies
Instructor: Thomas Skotnicki, STMicroelectronics
Introductions Historical Review of LP CMOS Engineering Mobility Electrostatics – Benchmarking Device Structures Inverter Delay – LP Specific Case - Effective Current - Load Capacitance - Impact of DIBL Benchmarking Bulk Planar, SOI and DG/FinFET Variability – Sources, Requirements, Impact LP Design Issues and Trends Perspective
Less-Power Design Instructor: Harry Veendrick, NanoCMOS-Training B.V.
Necessity of less-power design in all application areas Battery topics CMOS power sources and trends Relation between less-power technology and design solutions Leakage (Standby) power reduction techniques Active (Switching) power reduction techiques
Low Power Approaches for Memories Instructor: Akihiro Nitayama, Toshiba Corporation
Introduction - Memory System Requirements - Memory Positioning and Low Power Approach – Volatile Memories - Low Power SRAM - Low Power DRAM / FBC / NV-DRAM -Nonvolatile Memories - FeRAM - MRAM -Code/ Data Storage Memory - PRAM - NAND - BiCS/ReRAM 3D Chip Stacking Conclusion
BEOL, SiP, and 3D, Integration Technologies Instructor: James Jian-Qiang Lu, Rensselaer Polytechnic Institute
Introduction - Advances and Challenges in Interconnects and System Integrations - 3D Integration Category 3D Packaging (SiP, PoP) - System-in-Packaging Advances - Future Trends 3D Integration and Through-Strata-Vias (TSVs) - Technology Platforms - Key Unit Technologies - Advantages and Issues 3D Opportunities for Low Power/Low Energy Applications - 3D Integration Options - Perspectives
Emerging Device Concepts Instructor: H.S. Philip Wong, Stanford University
Circuit requirements: Performannce Benchmarking and Requirements, Circuit Level Optimization, CMOS Baseline iMOS Tunnel FET Carbon Nanotube Transistors Graphene Transistors Nanoelectromechanical (NEM) Relay
Scaling Challenges: Device Architectures, New Materials, and Process Technologies
Sunday, December 6, 9:00 a.m. - 5:30 p.m.
Key Ballrooms 8, 11 and 12
Going forward the industry faces unprecedented scaling challenges in device architecture, materials, process modules, and lithography to continuation Moore's law and cost reductions. The best technology direction for sub 32nm technologies nodes is highly uncertain in many areas some of which are high k/metal gate stack materials and process integration flow, planar versus non-planar MOSFET device structures, optical, EUV and double patterning, and in the area of new materials such as SiGe, SiC, low k spacers, and band edge metals. After nearly uniform adoption of unixial strained silicon for 90 to 32nm technology nodes, the industry is seeing more divergence in current 32nm logic IDM and foundry offerings and future plans. To help guide us through this uncertain time, this short course brings the leading technologist from industry and academia to provide insight and likely solutions to address the significant scaling challenges for 22 and 15 nm logic technologies.
The first lecture by IBM Fellow Ghavam Shahidi covers the limits of a bulk or SOI planar MOSFETs and the likely structures to be used for sub 32nm logic technologies. Next, Thomas Hoffmann of IMEC will share his insight into the industry status and future direction for high K dielectrics and metal gates covering both materials and process integration issues. The third talk is by Prof. Ken Uchida is on channel resistance, physics of mobility enhancement techniques and implementations issue for advance nodes. The forth talk is by Applied Material Sr. VP Hans Stork on key process modules for 32nm and beyond technologies node. The final talk is on the hot topic of limits of optical lithography and the status of EUV by Burn Lin of TSMC.
Introduction and Overview
Instructor: Scott Thompson, University of Florida
Device Architecture: Ultimate Planar CMOS Limit and Sub 32nm Device Options Instructor: Ghavam Shahidi, IBM Corp.
Challenges/Solutions Planar Bulk and SOI Scaling Planar Bulk and SOI Limit MuGFET and future device structures Insight and future direction
High K / Metal Gates: Industry Status and Future Direction Instructor: Thomas Hoffmann, IMEC
Performance Benefits I or C? Integration/Material Challenges Gate last or first integration flow? HK/MG scaling Insight and future direction
Channel Resistance: Mobility Enhancement Techniques Instructor: Ken Uchida, Tokyo Institute of Technology
Physics of Strained Si Process strain for planar device & MuGFET Implementation issues for advance nodes SiC and SiGe embedded stressors Orientation and process strain co-optimization New material- III-V/Ge Insight and future direction
Advanced Process Modules: "Key Process Technology for 32nm and Beyond" Instructor: Hans Stork, Applied Materials
Issues/requirements/solutions for chemical mechanical polish Lithography enhancing films Profile and high aspect ratio etch Plasma and ultra shallow Implant technology SiGe and SiC material issues Thermal processing millisecond flash and laser annealing Insight and future direction
Lithography: Limits of Optical Lithography and Status of EUV Instructor: Burn Lin, TSMC
Limits of Optical Lithography Issues status of Double-Patterning Requirements for OPC EUV assessment and status Layout Design Rules Insight and future direction