Session 14: Process Technology – Advanced 3D Technology and Processing

Tuesday, December 8, 9:00 a.m.
Key Ballroom 6

Co-Chairs: Xiaomeng Chen, IBM
Kyoungsub Shin, Samsung

9:00 a.m.
Introduction

9:05 a.m.
14.1  Advances in 3D CMOS Sequential Integration, P. Batude, M. Vinet, A. Pouydebasque, C. Le Royer, B. Previtali, C. Tabone, J.-M. Hartmann, L. Sanchez, L. Baud, V. Carron, A. Toffoli, F. Allain, V. Mazzocchi, D. Lafond, N. Bouzaida, O. Thomas, O. Cueto, A. Amara*, S. Deleonibus, O. Faynot, CEA LETI MINATEC, *ISEP

For the first time, 3D sequential CMOS integration turns up to be an actual competitor for sub 22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si active layer are obtained. Thermally robust bottom salicide goes through the whole top FET process without any significant sheet resistance degradation. The low temperature integration of raised source and drain for top layers is demonstrated. A decrease by 4Å of the Equivalent Oxide Thickness is measured when low thermal budget process is implemented. The electrostatic coupling between stacked FETs is demonstrated thanks to ultra thin inter layer dielectric thickness of 60nm. It leads to a threshold voltage shift of 130mV enabling SRAM stabilization.

9:30 a.m.
14.2  IThree-Dimensional Integration Technology Based on Reconfigured Wafer-to-Wafer and Multichip-to-Wafer Stacking Using Self-Assembly Method, T. Fukushima, E. Iwata, Y. Ohara, K.-W. Lee, J. Bea, T. Tanaka, M. Koyanagi, Tohoku Univesity

We demonstrated new 3D integration using reconfigured and direct self-assembled multichip-to-wafer stacking . In these 3D integration, key technologies of liquid pull-down, selective hydrophilzing, and super hydrophobic technologies were developed. High alignment accuracy of 200 nm was obtained by the self-assembly with water. Furthermore, chips with microbumps were successfully self-assembled and directly bonded without thermal compression. They showed good electrical characteristics.

9:55 a.m.
14.3  Enabling 3D-IC Foundry Technologies for 28 nm Node and Beyond: Through-Silicon-Via Integration with High Throughput Die-to-Wafer Stacking, D.Y. Chen, W.C. Chiou, M.F. Chen, T.D. Wang, K.M. Ching, H.J. Tu, W.J. Wu, C.L. Yu, K.F. Yang, H.B. Chang, M.H. Tseng, C.W. Hsiao, Y.J. Lu, H.P. Hu, Y.C. Lin, C.S. Hsu, W.S. Shue, C.H. Yu, TSMC

High density through-silicon-via and cost-effective 3D die-to-wafer integration scheme are proposed as foundry solutions for CMOS chips at 28 nm node and beyond. Key processes include: TSV formation, extreme thinning and die-to-wafer assembly. The impact of extreme thinning on device Vth,sat, leakage, and Ion-Ioff characteristics of bulk CMOS devices with and without e-SiGe/CESL stressors has been minimized. The presence of TSV caused no significant degradation in Cu/ELK reliability. These excellent characteristics suggest the 3D-IC processes are promising and suitable for adoption in next generation integrated circuits and interconnects.

10:20 a.m.
14.4  3D Stacked ICs Using Cu TSVs and Die to Wafer Hybrid Collective Bonding, G. Katti , A. Mercha, J. Van Olmen , C. Huyghebaert, A. Jourdain, M. Stucchi, M. Rakowski, I. Debusschere, P. Soussan, W. Dehaene, K. De Meyer, Y. Travaly, E. Beyne, S. Biesemans, B. Swinnen, IMEC

We report 3D circuits obtained by a 3D Stacked IC approach using both Cu through Silicon Vias (TSV) First and Die-to-Wafer Hybrid Collective bonding. The CMOS devices integrity and a lumped RC TSV models are also validated through model hardware correlation using 3D RO with inverters on top tiers and bottom wafer alternatively connected through 40 TSVs.

10:45 a.m.
14.5  Impact of Remnant Stress/Strain and Metal Contamination in 3D-LSIs with Through-Si Vias Fabricated by Wafer Thinning and Bonding, M. Murugesan, J.C. Bea, H. Kino, Y. Ohara, M. Kojima, A. Noriki, K.W. Lee, K. Kiyoyama, T. Fukushima, H. Nohira*, T. Hattori, E. Ikenaga**, T. Tanaka, M. Koyanagi, Tohoku University, *Musashi Institute of Technology, **JASRI

The remnant stress due to wafer thinning process in extremely thin (10 micron) Si wafers was investigated by micro-Raman Spectroscopy andX-ray Photo Electron Spectroscopy, and the data revealed that chmical mechanical polishing method was the best among all the stress relieving method studied. From the electrical characteristics of n- and p-MOSFET, we have deduced a 3% change in the ON current ratio when the 50 micron thick wafer subjected to bend few microns. The deleterious role of inevitable metal contamination on the device performance was studied by determining the minority-carrier-life- time in MOS capacitor after accelerated diffusion with Cu.

11:10 a.m.
14.6  Ultra Thinning 300-mm Wafer Down to 7-µm for 3D Wafer Integration on 45-nm Node CMOS using Strained Silicon and Cu/Low-k Interconnects,> Y. S. Kim, A. Tsukune, N. Maeda*, H. Kitada*, A. Kawai**, K. Arai**, K. Fujimoto^, K. Suzuki^, Y. Mizushima^^, T. Nakamura^^, T. Ohba*, T. Futatsugi, M. Miyajima, Fujitsu Microelectronics Limited, *University of Tokyo, **DISCO Corporation, ^Dai Nippon Printing, ^^Fujitsu Laboratories Ltd.

High performance 45-nm Node and its 3D integration employed aggressively thinned down to 7-µm of 300-mm wafer for the Wafer-on-a-Wafer (WOW) application has been succeeded for the first time. The impact of ultra thin wafer on strained transistors and Cu/low-k multilevel interconnects is described, and no degradation regarding electrical performance is found.