Session 14: Characterization, Reliability, and Yield - ESD/Memory Reliability

Tuesday, December 16, 9:00 a.m.
Continental Ballroom 6

Co-Chairs: Harald Gossner, Infineon Technologies AG
Alessandro Paccagnella, University of Padova

9:00 a.m.
Introduction

9:05 a.m.
14.1  ESD Qualification Changes for 45nm and Beyond (Invited), C. Duvvury, Texas Instruments Inc.

As the silicon technologies advance further into sub-50nm features sizes, the circuit demands for high-speed operation are continually making ESD into a challenging issue. This paper reviews the current perception about ESD and why there must be an immediate paradigm shift for the ESD qualification requirements.

9:30 a.m.
14.2  Impact of Strain on ESD Robustness of FinFET Devices, A. Griffoni, S. Thijs, C. Russ**, D. Tremouilles^, M. Scholz, D. Linten, N. Collaert, R. Rooyackers, C. Duvvury^^, H. Gossner**, G. Meneghesso*, G. Groeseneken, IMEC, *University of Padova, **Infineon Technologies AG, ^LAAS/CNRS, ^^Texas Instruments Inc.

The ESD performance of multi-gate NMOS devices is investigated in both active MOS-diode and parasitic-bipolar mode, highlighting the impact of strained SiN layers. Strain improves the ESD robustness up to 30 % in multi-fin FinFETs. A different failure mechanism is discovered in strained devices.

9:55 a.m.
14.3  Guard Ring Interactions and their Effect on CMOS Latchup Resilience, F. Farbiz, E. Rosenbaum, University of Illinois at Urbana-Champaign

Latchup resilience is studied by considering interactions between multiple carrier collectors and N or P-type guard rings. It is shown that P-type taps and guard rings have a deleterious effect on latchup. Physical explanations are provided based on measurements in 90 and 130nm technologies as well as extensive device simulations.

10:20 a.m.
14.4  A Novel Method For Evaluating Electron/Hole Mismatch In Scaled Split-Gate SONOS Memories, Y. Tsuji, M. Terai, S. Fujieda, T. Syo*, T. Saito*, K. Ando*, NEC Corporation, *NECEL Corporation

A new simple method for lateral charge profiling of split-gate SONOS memory was developed to separate trapped charge densities near and far from drain. Retention loss due to electron/hole mismatch is successfully reproduced with two hole components near and far from the drain that this method evaluates.

10:45 a.m.
14.5  Statistical Investigation of the Floating Gate Memory Cell Leakage through High-k Interpoly Dielectrics and Its Impact on Scalability and Reliability, B. Govoreanu, R. Degraeve, J. Van Houdt, G. Jurczak, IMEC

We investigate the floating gate cell leakage through high-k IPDs, using a statistical approach. Experimentally extracted trap distributions are used together with a newly developed Monte-Carlo leakage/retention simulator to study the impact of single- and multitrap leakage paths on scaled cells and predict the failure rate on Flash memory arrays.

11:10 a.m.
14.6  Neutron-Induced Soft Errors In Advanced Flash Memories, G. Cellere1, S. Gerardin1, M. Bagatin1, A. Paccagnella1, A. Visconti2, M. Bonanomi2, S. Beltrami2, P. Roche3, G. Gasiot3, R. Harboe Sorensen4, A. Virtanen5, C. Frost6, P. Fuochi7, C. Andreani8, G. Gorini9, A. Pietropaolo9, S. Platt10, 1Padova University, 2Numonyx R&D, 3STMicroelectronics, 4ESA/ESTEC, 5University of Jyvaskyla, 6Rutherford Appleton Laboratory, 7CNR-ISOF, 8Universita di Roma Tor Vergata, 9University di Milano, 10University of Central Lancashire

We demonstrate Soft Errors induced by atmospheric neutrons in Flash memories and we provide an explanation linked to the physics of the neutron-matter interaction. The neutron sensitivity is expected to increase for future technologies, but the Soft Error issue is and will be within the limit of ECC capabilities.