Session 25: IEDM Evening Panel Discussion

Tuesday, December 8, 8:00 p.m.
Key Ballrooms 8, 11 and 12

Organizer: Dimitri Antoniadis, MIT

"When and How Will the High Mobility Substrates Impact the Si Technology Roadmap”

The classical MOSFET scaling era has been over approximately since the 130 nm CMOS technology. While the cadence of geometric scaling has continued, new process elements (strain) and new materials (hi-K/metal gate) had to be introduced in order to provide improved transistor performance with scaling. In particular, strain has been very effective in increasing key carrier transport parameters, "thermal velocity" and mobility in and has resulted in significant improvement of nFETs and dramatic improvement of pFETs. But strained-Si is reaching its physical limits and alternative approaches are being sought to further enhance carrier transport properties via the introduction of "high-mobility" materials on Si. At this point, SiGe and Ge appear to be suitable candidates primarily for hole channels while various III-V materials are being investigated primarily for electron channels. The objective of this panel is to provide a perspective on the following:

1. What is a possible or likely scenario for the introduction of new channel materials in the 15 nm CMOS node? Is it possible with the currently anticipated geometric scaling cadence of gate-contacted pitch?
2. What are the key milestones that must be demonstrated before industry would invest heavily in developing this technology?
3. Is it possible that suppliers would be able to provide the necessary equipment for this materials integration? – Would need a supplier rep on the panel for this?
4. What are the likely show-stoppers for the introduction of this technology element?

Panelists:
Ghavam Shahidi, IBM
Robert Chau, Intel
Krishna Saraswat, Stanford University
Gene Fitzgerald, Massachusetts Institute of Technology
Yee-Chia Yeo, National University of Singapore
Tomas Skotnicki, STMicroelectronics
Shinichi Takagi, University of Tokyo