Session 27: Memory Technology – 3D Memory: Non-volatile Memory Architectures

Wednesday, December 9, 9:00 a.m.
Key Ballrooms 7, 9 and 10

Co-Chairs: Agostino Pirovano, Numonyx
Klaus Schuegraf, Applied Materials

9:05 a.m.
27.1  A Stackable Cross Point Phase Change Memory, D.C. Kau, S. Tang*, S. Lee, R. Dodge*, B. Klehn, J. Strand*, J.A. Kalb, A. Diaz*, N. Leung, J. Wu*, I.V. Karpov, T. Langtry*, J. Lee, C. Papagianni*, K.-W. Chang, H. Castro*, S. Erra, J. Hirst*, G. Spadini, Intel Corp., *Numonyx B.V.

A phase change memory cell is built by coupling PCM with OTS (PCMS) and integrated in a true cross point array. Multiple layers of PCMS arrays can be stacked over CMOS circuits. This fast, durable, and dense memory for random access and storage applications provides a promising, scalable NVM technology.

9:30 a.m.
27.2  Monolithic Integration of NEMS-CMOS with Mechanically Flip-Flopped Fin Memory, J.-W. Han, J.-H. Ahn, M.-W. Kim, J.-B. Yoon, Y.-K. Choi, KAIST

Independent-gate FinFET and mechanically flip-flopped fin NEMS memory is co-fabricated with CMOS process. The proposed NEMS memory is featured by the laterally actuated channels with various widths and a 10nm air-gap thickness, which provides a sensing current window of 10⁷, data retention time over 10⁴ sec, and endurance over 10³ cycles in air.

9:55 a.m.
27.3  Optimal Device Structure for Pipe-shaped BiCS Flash Memory for Ultra High Density Storage Device with Excellent Performance and Reliability, M. Ishiduki, Y. Fukuzumi, R. Katsumata, M. Kito, M. Kido, H. Tanaka, Y. Komori, Y. Nagata*, T. Fujiwara, T. Maeda, Y. Mikajiri, S. Oota, M. Honda, Y. Iwata, R. Kirisawa, H. Aochi, A. Nitayama , Toshiba Corporation, *Toshiba Information Systems Corporation

An asymmetric source/drain profile for select gate and metal salicided control gate are successfully realized on Pipe-shaped Bit Cost Scalable (P-BiCS) Flash memory to achieve data storage device with excellent performance and reliability.

10:20 a.m.
27.4  Study of Sub-30nm Thin Film Transistor (TFT) Charge-Trapping (CT) Devices for 3D NAND Flash Application, T.-H. Hsu, H.-T. Lue, C.-C. Hsieh, E.-K. Lai, C.-P. Lu, S.-P. Hong, M.-T. Wu, F.H. Hsu, N.Z. Lien, J.-Y. Hsieh, L.-W. Yang, T. Yang, K.-C. Chen, K.-Y. Hsieh, R. Liu, C.-Y. Lu, Macronix International Co. Ltd.

Sub-30nm TFT CT NAND flash devices have been extensively studied. Our results show that as TFT devices scale down to sub-30nm, the DC characteristics approach those of the bulk devices. However, grain boundaries only affects the DC characteristics but does not impact the memory window. A sub-30 nm TFT BE-SONOS NAND device with MLC capability and good retention is demonstrated.

10:45 a.m.
27.5  One-Transistor Nonvolatile SRAM (ONSRAM) on Silicon Nanowire SONOS, S.-W. Ryu, J.-W. Han, D.-I. Moon, Y.-K. Choi, KAIST

We have developed One-transistor Nonvolatile SRAM (ONSRAM) on a silicon nanowire (SiNW) SONOS. The nonvolatile memory (NVM) property was constructed by employing O/N/O gate dielectric stacks as an electron storage node, and SRAM operation is stemmed from latch phenomena of a floating body in SiNW. An abrupt inverter switching, superior sensing current (>23μA), and high interference immunity between SRAM and NVM approve the feasibility for the scheme of ONSRAM.

11:10 a.m.
27.6  A Stacked SONOS Technology, Up to 4 Levels and 6nm Crystalline Nanowires, with Gate-All-Around or Independent Gates (ΦFlash), Suitable for Full 3D Integration, A. Hubert, E. Nowak, K. Tachi, V. Maffini-Alvaro, C. Vizioz, C. Arvet**, J.-P. Colonna, J.-M. Hartmann, V. Loup, L. Baud, S. Pauliac, V. Delaye, C. Carabasse, G. Molas, G. Ghibaudo*, B. De Salvo, O. Faynot, T. Ernst, CEA-LETI MINATEC, *IMEP-LAHC INPG MINATEC, **STMicroelectronics

We present the first experimental study of 3D SONOS memory with 4-level crystalline stacked nanowire channels. Results with 6nm nanowires show high programming windows with excellent retention. The technology is also integrated in independent double gate memory (ΦFlash). The process to fully disconnect the levels for 3D integration is discussed.

11:35 a.m.
27.7  Future Directions of Non-Volatile Memory in Compute Applications (Invited), A. Fazio, Intel Corp.

NAND's new position in the compute memory hierarchy imposes new considerations for scaling to smaller lithography nodes and tightly links NAND with the external controller. Likewise, widespread acceptance of future NVM in the compute memory hierarchy will be determined by ability to meet both cost and performance criteria.