Session 30: Quantum, Power, and Compound Semiconductors Devices - Heterostructure High-Speed Devices

Wednesday, December 17, 9:00 a.m.
Continental Ballroom 5

Co-Chairs: Suman Datta, Pennsylvania State University
Rebecca Nicolic, Lawrence Livermore National Laboratory

9:00 a.m.
Introduction

9:05 a.m.
30.1  30 nm E-mode InAs PHEMTs for THz and Future Logic Applications, D.-H. Kim, J.A. del Alamo, Massachusetts Institute of Technology We have demonstrated 30 nm E-mode InAs PHEMTs with outstanding logic performance, scalability, record f_T in E-mode devices, and record combination of f_T and f_max above 600 GHz.

9:30 a.m.
30.2  AlInAs/GaInAs mHEMTs on Silicon Substrates by MOCVD (Invited), K.M. Lau, C.W. Tang, H. Li, Z. Zhong, Hong Kong University of Science and Technology

Device quality metamorphic A_l0.50In_0.50As/Ga_0.47In_0.53As HEMT structures have been successfully grown by MOCVD on silicon substrates for the first time, with 2-DEG mobilities > 4500 cm²/V-s and sheet carrier densities >7 x 1012 cm^-2. 1.3- μm gated transistors (Gm = 274mS/mm) demonstrated f_T and f_max of 20 and 23GHz, respectively.

9:55 a.m.
30.3  High-Performance 40nm Gate Length InSb P-Channel Compressively Strained Quantum Well Field Effect Transistors For Low-Power (VCC=0.5V) Logic Applications, M. Radosavljevic, T. Ashley*, A. Andreev*, S.D. Coomber*, G. Dewey, M.T. Emeny*, M. Fearn*, D.G. Hayes*, K.P. Hilton*, M.K. Hudait, R. Jefferies*, T. Martin*, R. Pillarisetty, W. Rachmady, T. Rakshit, S.J. Smith*, M.J. Uren*, D.J. Wallis*, P.J. Wilding*, R. Chau, Intel Corporation, *QinetiQ

We demonstrate for the first time a high-speed and low-power III-V p-channel QWFET using a compressively strained InSb QW structure, which achieves cut-off frequency (f_T) of 140GHz at transistor gate length (LG) of 40nm and supply voltage of 0.5V. This represents the highest fT ever reported for III-V p-channel FETs.

10:20 a.m.
30.4  SiGe HBT Module with 2.5 ps Gate Delay, A. Fox, B. Heinemann, R. Barth, D. Bolze, J. Drews, U. Haak, D. Knoll, B. Kuck, R. Kurps, S. Marschmeyer, H.H. Richter, H. Rucker, P. Schley, D. Schmidt, B. Tillack, G. Weidner, C. Wipf, D. Wolansky, Y. Yamamoto, IHP

A novel, double-polysilicon, three-mask SiGe HBT module with selective base epitaxy is presented. By this technology a low-parasitic link between the internal and external base is formed resulting in best-in-class CML ring oscillator gate delays of 2.5ps.

10:45 a.m.
30.5  Fabrication and Characterisation of Strained Si Heterojunction Bipolar Transistors on Virtual Substrates, S. Persson, M. Fjer, E. Escobedo-Cousin, G. Malm*, Y.-B. Wang*, P.-E. Hellström*, M. Östling*, E. Parker**, S.H. Olsen and A.G. O'Neill, Newcastle University, *IMIT, KTH, **University of Warwick

Strained Si HBTs have been demonstrated for the first time with maximum current gain of 3700 on a relaxed Si_0.85Ge_0.15 virtual substrate, strained Si emitter and Si_0.7Ge_0.3 base. Pseudomorphic SiGe HBTs and Si control BJTs were also manufactured in parallel having current gains of 334 and 135 respectively.

11:10 a.m.
30.6  Record PVCR GaAs-based Tunnel Diodes Fabricated on Si Substrates using Aspect Ratio Trapping, S.L. Rommel, D. Pawlik, P. Thomas, M. Barth, K. Johnson, S.K. Kurinec, Z. Cheng*, J. Li*, J.S. Park*, J. Hydrick*, N. Bai*, M. Carroll*, J. Fiorenza*, A. Lochtefeld*, A. Seabaugh**, Rochester Institute of Technology, *Amberwave Systems Corporation, **University of Notre Dame

Growth of high quality GaAs on Si is produced by Aspect Ratio Trapping followed by metalorganic chemical vapor deposition to grow n+GaAs/n+InGaAs/p+GaAs Esaki interband tunnel diodes. Tunnel diodes fabricated on this material have almost twice the room-temperature peak-to-valley current ratio (PVCR) of the best GaAs diodes ever reported; a PVCR of 46 at room temperature is achieved.

11:35 a.m.
30.7  Single-Electron Circuit for Stochastic Sata Processing Using nano-MOSFETs, K. Nishiguchi, A. Fujiwara, NTT Corporation A MOSFET-based circuit utilizing single electrons is demonstrated. The behavior of individual electrons randomly passing through a silicon-on-insulator MOSFET, which is monitored by an electrometer in real time, is used for random-number generation suitable for a data processing that stochastically extracts the optimum solution.