Session 31: MMemory Technology - Phase-Change Memory, RRAM and DRAM

Wednesday, December 12, 1:30 p.m.
Continental Ballroom 5

Co-Chairs: Hsiang-Lan Lung, Macronix International Co., Ltd.
Takashi Kobayashi, Hitachi, Ltd.

1:30 p.m.
Introduction

1:35 a.m.
31.1  A Thermally Robust Phase Change Memory by Engineering the Ge/N Concentration in (Ge_,N)_xSb_yTe_z Phase Change Material, H.Y. Cheng, J.Y. Wu, R. Cheek*, S. Raoux*, M. BrightSky*, D. Garbin**, S. Kim*, T.H. Hsu*, Y. Zhu, E.K. Lai, E. Joseph*, A. Schrott*, S.C. Lai, A. Ray*, H.L. Lung, C. Lam*, Macronix International Co., Ltd., *IBM TJ Watson Research Center, **Turin Polytechnic University

Phase change memory (PCRAM) is an ideal embedded memory due to its simple BEOL process and low voltage operation. Industrial and automotive applications of PCRAM, however, have not been realized because of poor high temperature properties of the conventional Ge₂Sb₂Te₅ phase-change material [1-3]. We have previously reported a special Ge_xSb_yTe_z material along the Ge and Sb₂Te₃ tie line that showed superior high temperature performance. In this work we have further enhanced our previous "golden" material by incorporating nitrogen and engineering the Ge/N concentration. In order to rapidly explore a range of new materials a fast method to test retention behavior by laser melt-quenching is adopted which yields retention data on blanket films consistent with device results. A new material with special Ge/N concentration with excellent high temperature retention is discovered. The new material demonstrated nearly 100% yield in a 256 Mb test chip after 160 °C, 84 hrs baking, with projected 10-year retention at 120 °C. (> 9,000 years at 85 °C.)

2:00 p.m.
31.2  Non-Arrhenius Pulse-Induced Crystallization in Phase Change Memories, N. Ciocchini, M. Cassinerio, D. Fugazza, D. Ielmini, DEI, Politecnico di Milano and IU.NET ,p>This work provides the first evidence for non-Arrhenius crystallization in phase change memory (PCM). Crystallization data in the thermal (annealing) and set (pulse-induced) regimes are compared by a filamentary conduction model of the PCM after threshold switching. Results show different activation energies in the two regimes, thus evidencing non-Arrhenius behavior.

2:25 p.m.
31.3  Engineering Grains of Ge₂Sb₂Te₅ for Realizing Fast-Speed, Low-Power, and Low-Drift Phase-Change Memories with Further Multilevel Capabilities, W.J. Wang, D. Loke, L.T. Law, L.P. Shi, R. Zhao, M.H. Li, L.L. Chen*, H.X Yang, Y.C. Yeo*, A.O. Adeyeye*, T.C. Chong**, A.L. Lacaita***, A*STAR, *National University of Singapore, **Singapore University of Technology and Design, ***Politecnico di Milano and IFN-CNR Milano

Grain-engineered Ge₂Sb₂Te₅ was exploited to control the crystallization kinetics and electrical properties of PCM, resulting in a 120% higher SET speed with respect to conventional scaling. Good stability (140°C), 30% RESET power reduction, and 2X lower resistance drift were also achieved. A multilevel (4 state/2-bit) cell was further demonstrated.

2:50 p.m.
31.4  A Low Power Phase Change Memory Using Low Thermal Conductive Doped-Ge₂Sb₂Te₅ with Nano-Crystalline Structure, T. Morikawa, K. Akita, T. Ohyanagi, M. Kitamura, M. Kinoshita, M. Tai, N. Takaura, bLow-power Electronics Association and Project

A new phase change memory of 68% lower reset current is demonstrated using nano-crystalline doped-Ge2Sb2Te5 with low thermal conductivity. Endurance of >1×10⁷ cycles and enhanced crystallization temperature (~ 215 °C) are also achieved. Nano-crystalline GST makes it possible to design 4F² cross-point cells with simple bottom electrode structure.

3:15 p.m.
31.5  Sb-Doped GeS₂ as Performance and Reliability Booster in Conductive Bridge RAM, E. Vianello, G. Molas, F. Longnos*, P. Blaise, E. Souchier, C. Cagli, G. Palma, J. Guy, M. Bernard, M. Reyboz, G. Rodriguez, A. Roule, C. Carabasse, V. Jousseaume, S. Maitrejean, G. Reimbold, B. De Salvo, F. Dahmani*, P. Verrier*, D. Bretegnier*, J. Liebault*, CEA-Leti, Minatec, *ALTIS Semiconductor,

In this work, for the first time at our knowledge, the improvement of chalcogenide-based CBRAM performance and reliability by Sb doping of the GeS₂ electrolyte is presented. An original analysis, based on in-depth physico-chemical characterization, device electrical measurements, empirical model and first principle calculations, is shown. We argue that optimized ~10% Sb doping in the GeS2 electrolyte allows to achieve SET speed of 30ns at 2.2V (i.e. 0.66pJ SET programming power), while assuring 10 years data retention at 125°C, >10⁵ cycling and high robustness to Sn-Pb soldering profile. Finally, the improved thermal stability of the filament in the GeS₂-Sb matrix is clearly elucidated by means of molecular dynamics.

3:40 p.m.
31.6  High-K Metal Gate Contact RRAM (CRRAM) in Pure 28nm CMOS Logic Process, W.C. Shen, C.Y. Mei, Y.-D. Chih, Y.-C. King, C.J. Lin, National Tsing-Hua University, *Taiwan Semiconductor Manufacturing Company

A new high density Contact RRAM (CRRAM) cell realized in pure high-k metal gate 28nm CMOS logic process with a very small 35nm x 35nm resistive contact hole has been fabricated without extra masking or process step. This study reports the first time of a manufacturable tiny resistive node of RRAM cell on a 28nm CMOS logic platform and fully compatible with high-k metal gate processes.

4:05 p.m.
31.7  Highly Endurable Floating Body Cell Memory: Vertical Biristor, D.-I. Moon, S.-J. Choi, J.-Y. Kim, S.-W. Ko, M.-S. Kim, J.-S. Oh*, G.-S. Lee*, M.-H. Kang*, Y.-S. Kim*, J.-W. Kim*, Y.-K. Choi, KAIST, *National NanoFab Center

An open-base BJT named 'biristor', which is an n-p-n vertical silicon pillar, is demonstrated for high speed volatile memory applications. A 4F² cross-bar memory cell array is realized by the unidirectional operation of the two-terminal biristor. Due to the gate-less structure, the biristor shows excellent endurance of up to 10¹⁶.

4:30 p.m.
31.8  Active Width Modulation (AWM) for Cost-Effective and Highly Reliable PRAM, D. Ha, K.W. Lee, K.R. Sim, J.H. Yu, S.J. Ahn, S.Y. Kim, T.H. An, S.H. Hong, S.K. Kim, J.W. Lee, B.C. Kim, G.H. Koh, S.W. Nam, G. Jeong, C. Chung, Samsung Electronics Co. Ltd.

This paper presents, for the first time, the Active Width Modulation (AWM) technology which compensates a string resistance with the active widths of local Y selectors for the purpose of increasing the number of cells-per-string (CPS). The AWM is demonstrated using 58 nm 512 Mb PRAM with 32 CPS instead of 8 CPS [1], which can reduce the chip size by 4.3%. Also, the systematic variability of a program current is reduced from 17.8% to 0.82%, and that of a write energy from 47.9% to 2.0%. Both write endurance and disturbance of >1M cycles are achieved for 512 Mb PRAM. The AWM can be further applied to increase CPS to 64 or 128, together with the reduction of a reset current for sub-40 nm PRAM technology and so on.