Session 34: Memory Technology - Nanoscale Poly-FG and Charge Trap Flash Non-Volatile Memories

Wednesday, December 17, 1:30 p.m.
Grand Ballroom A

Co-Chairs: Tejas Krishnamohan, Intel Corporation
Jong-Ho Lee, Kyungpook National University

1:30 p.m.
Introduction

1:35 p.m.
34.1  Floating Gate Super Multi Level NAND Flash Memory Technology for 30nm and Beyond, T. Kamigaichi, F. Arai, H. Nitsuta, M. Endo, T. Murata, H. Takekida, T. Izumi, K. Uchida, T. Maruyama, I. Kawabata, Y. Suyama, A. Sato, K. Ueno, H. Takeshita, Y. Joko, S. Watanabe, Y. Liu, H. Meguro, A. Kajita, Y. Ozawa, and T. Watanabe, S. Sato*, H. Tomiie*, Y. Kanamaru*, R. Shoji*, C.H. Lai*, M. Nakamichi*, K. Oowada*, T. Ishigaki*, G. Hemink*, D. Dutta*, Y. Dong*, C. Chen*, G. Liang*, M. Higashitani*, J. Lutze*, Toshiba Corporation, *SanDisk Corporation

Floating Gate NAND Flash Memory Technology for 30nm and beyond has been successfully developed. Wide program/erase window, tight natural V_th distribution, and good cell reliabilities such as program disturb, rogram/erase endurance and data retention are successfully demonstrated, which are essential to realize Super MLC.

2:00 p.m.
34.2  Novel Model For Cell - System Interaction (MCSI) In NAND Flash, C. Friederich, J. Hayek, A. Kux, T. Müller**, N. Chan**, G. Koebernik, M. Specht, D. Richter, D. Schmitt-Landsiedel*, Qimonda Flash GmbH, *Technical University Munich, **Qimonda Dresden GmbH & Co.

For the first time a stochastic model of the program operation in NAND Flash memories is proposed. The model incorporates intrinsic noise effects on the cells' threshold voltage (V_th) distribution in incremental step pulse programming (ISPP) schemes. An excellent match with experimental data at 48 nm ground rule is shown.

2:25 p.m.
34.3  Scaling Trends For Random Telegraph Noise In Deca-Nanometer Flash Memories, A. Ghetti, C. Monzio Compagnoni*, F. Biancardi*, A.L. Lacaita*, S. Beltrami, L. Chiavarone, A.S. Spinelli*, A. Visconti, Numonyx R&D, *Politecnico di Milano

In this work we present a thorough investigation of RTN scaling trends for both NAND and NOR Flash memories, including experimental and modeling results. A comprehensive analysis of RTN dependence on cell parameters is presented. Results are of utmost importance to derive RTN design margins in next generation technology nodes

2:50 p.m.
34.4  10 nm Bulk-Planar SONOS-type Memory with Double Tunnel Junction and Sub-10 nm Scaling Utilizing Source to Drain Direct Tunnel Sub-threshold, R. Ohba, Y. Mitani, N. Sugiyama, S. Fujita, Toshiba Corporation

10nm SONOS-type device with double tunnel junction, where Si nanocrystals are lying between double tunnel oxides, shows an excellent non-volatility in low w/e voltages. 8nm double junction SONOS shows a reliable performance by realizing S/D direct tunnel sub-threshold. Further device scaling and improvement are possible utilizing S/D direct tunnel sub-threshold. Double junction SONOS is a promising candidate in sub-10nm region.

3:15 p.m.
34.5  Good 150°C Retention and Fast Erase Charge-Trapping-Engineered Memory with Scaled S_i3N₄, S.H. Lin, A. Chin*, F.S. Yeh, S.P. McAlister**, National Tsing-Hua University, *National Chiao-Tung University, **National Research Council of Canada

At 150°C under fast 100μs and 16V P/E, the charge-tapping-engineered memory with very thin 5nm Si₃N₄ shows good device integrity of large initial 5.6V and 3.8V 10-year extrapolated retention. These are much better than the initial 3.3V and 1.7V 10-year data for similar structure without extra 0.9nm EOT deep-trapping HfON.

3:40 p.m.
34.6  Sub-50nm DG-TFT-SONOS - The Ideal Flash Memory for Monolithic 3-D Integration, A.J. Walker, Schiltron Corporation

A revolutionary 3-D stackable sub-50nm double-gate TFT SONOS technology is reported with strings of up to 64 cells consisting of the smallest TFT's to date. Read- and program-pass disturbs have been extinguished. Excellent endurance and retention are shown. Monolithic 3-D integration is ensured through ~zero S/D diffusion.

4:05 p.m.
34.7  Disturbless Flash Memory Due to High Boost Efficiency on BiCS Structure and Optimal Memory Film Stack for Ultra High Density Storage Device, Y. Komori, M. Kido, M. Kito, R. Katsumata, Y. Fukuzumi, H. Tanaka, Y. Nagata*, M. Ishiduki, H. Aochi, A. Nitayama, Toshiba Corporation, *Toshiba Information Systems Corporation

Program and erase operation on NAND-string of Bit-Cost Scalable (BiCS) flash memory has been successfully achieved. High boost efficiency of floating pillars and ONON (block oxide/charge SiN/tunnel oxide/tunnel SiN) structure as a memory film stack improve disturbance characteristics low enough to realize tera-bit density of three dimensional flash memory.