Session 34: CMOS Devices - Advanced Device Structures

Wednesday, December 12, 1:30 p.m.
International Ballroom Center

Co-Chairs: Chih-Sheng Chang, TSMC
Akira Hokazono, Toshiba

1:30 p.m.
Introduction

1:35 p.m.
34.1  Observation of Mobility Enhancement in Strained Si and SiGe tri-gate MOSFETs with Multi-nanowire Channels Trimmed by Hydrogen Thermal Etching, T. Tezuka, E. Toyoda*, S. Nakaharai, T.Irisawa, N. Hirashita, Y. Moriyama, N. Sugiyama, N. Taoka**, Y. Yamashita**, O. Kiso**, M. Harada, T. Yamamoto and S. Takagi**, MIRA-ASET, *Covalent Materials Corp., **MIRAI-AIST

Strained Si and SiGe tri-gate nanowire MOSFETs with significantly reduced line-edge roughness and smooth sidewalls were fabricated by a novel anisotropic thermal etching in H₂ atmosphere. Carrier mobility measurements revealed strain-induced mobility enhancement by factors around 2 and the impact of the surface roughness scattering and sidewall shapes.

2:00 p.m.
34.2  Investigation of Nanowire Size Dependency on TSNWFET, S.D. Suk, M. Li, Y-Y Yeoh, K. Yeo, K.H. Cho, I.K. Ku**, H. Cho*, WJ Jang *, D-W Kim, D. Park, and W-S Lee, Samsung Electronics

Nanowire size (d_NW) dependency of various electrical characteristics on gate all around Twin Silicon Nanowire MOSFET (TSNWFET) is investigated to understand overall performance of nanowire transistor deeply. When dNW decreases, current drivability (I_ON) normalized by circumference at the same V_G-V_TH improves and maximizes at d_NW of 4nm. And mobility is also estimated with capacitance and series resistance. All the experimental investigation shows that dNW of 4nm is the best point to maximize the volume inversion effect on gate all around nanowire MOSFET.

2:25 p.m.
34.3  New Self-Aligned Silicon Nanowire Transistors on Bulk Substrate Fabricated by Epi-Free Compatible CMOS Technology: Process Integration, Experimental Characterization of Carrier Transport and Low Frequency Noise, Y. Tian, R. Huang, Y. Wang, J. Zhuge, R. Wang, J. Liu, X. Zhang, Y. Wang, Peking University

A new method to fabricate self-aligned silicon-nanowire transistors (SNWTs) has been realized on bulk substrate by fully epi-free compatible CMOS technology. SNWTs exhibit excellent immunity of short-channel effects and achieve high Ion/Ioff ratio of 2.6x108. The ballistic efficiency and low frequency noise of SNWTs are investigated for the first time.

2:50 p.m.
34.4  Experimental Investigation on Superior PMOS Performance of Uniaxial Strained <110> Silicon Nanowire Channel By Embedded SiGe(e-SG) Source/Drain, M. Li, K.H. Yeo, Y-Y Yeoh, S.D. Suk, K.H. Cho, D-W Kim, D Park, and W-S Lee, Samsung Electronics Co., Ltd.

Strained silicon nanowire transistor with embedded SiGe source/drain is investigated for the first time on experiments. About 85% PMOS performance gain is obtained by e-SG. Under compressive stress condition, changing nanowire direction from <100> to <110> gives 136% PMOS performance improvement. By both performance boosters, superior PMOSFET to NMOSFET has been presented with silicon nanowire transistors.

3:15 p.m.
34.5  A Novel Body Effect Reduction Technique to Recessed Channel Transistor Featuring Partially Insulating Layer Under Source and Drain : Application to Sub-50nm DRAM Cell, J-M Park, S-O Sohn, J-S Park, J-B Lee, S. Yamada, W. Yang, D. Park, Samsung Electronics Co.

We have successfully fabricated fully integrated advanced RCAT (Recess Channel Array Transistor) featuring partially insulating oxide layers in bulk Si substrate, named Partially-insulated-RCAT (Pi-RCAT). The Pi-RCAT demonstrated superior characteristics in body effect, subthreshold slope (SW) and higher current drivability in comparison with conventional RCAT. Furthermore, in the Partially-insulated-STI (Pi-STI) of core and peripheral structure formed simultaneously, well isolation characteristic is improved remarkably due to increase of effective isolation path. In this paper, Pi-RCAT is proved to be effective for the scalability and drivability of RCAT, and Pi-STI is suitable for the improvement of chip shrinkage efficiency.

3:40 p.m.
34.6  Ultra-Low Leakage Silicon-on-Insulator Technology for 65 nm Node and Beyond, J. Cai, A. Majumdar, D. Dobuzinsky*, T.H. Ning, S. Koester, and W. Haensch, IBM Research, *IBM SRDC

We report 65 nm ground-rule, partially depleted, low-power silicon-on-insulator (LPSOI) CMOS devices with total leakage current I_OFF down to 10 pA/um at supply voltage V_DD = 1.2 V. NFET/PFET drive current I_DSAT = 550/250 µA/µm at I_OFF = 100 pA/µm and gate length L_G ~ 55 nm are achieved with a single tensile liner film. Innovative junction engineering techniques such as low-damage junction pre-amorphization implants (PAI), source-side PAI, high-energy halo, and drain-side tilted source/drain (S/D) implants are evaluated for their effectiveness in minimizing SOI floating body effect for low leakage design. Our result suggests that there are no fundamental limits for low leakage application of SOI.