Session 34: Memory Technology – Flash Memory

Wednesday, December 9, 1:30 p.m.
Key Ballrooms 7, 9 and 10

Co-Chairs: Tzu-Ning Fang, Spansion
Jan Van Houdt, IMEC

1:30 p.m.
Introduction

1:35 p.m.
34.1  Investigation of Ballistic Current in Scaled Floating-Gate NAND FLASH and a Solution, S. Raghunathan, T. Krishnamohan, K. Parat*, K. Saraswat, Stanford University, *Intel Corp.

For the first time, we investigate the ballistic transport that occurs across ultra-thin (fabricated upto 7nm) poly-Si FGs in scaled NAND FLASH and experimentally determine mean-free-path. We also demonstrate a solution using ultra-thin metal FG(fabricated upto 3nm) and show 1000X lesser ballistic current than poly-Si of same thickness.

2:00 p.m.
34.2  The New Program/Erase Cycling Degradation Mechanism of NAND Flash Memory Devices, A. Fayrushin, K.S.Seol, J.H. Na, S.H. Hur, J.D. Choi, K. Kim, Samsung Electronics

Program/erase degradation model based on non-uniformly distributed trapped charge in tunnel oxide is suggested to explain midgap voltage and subthreshold slope change observed during program/erase cycling of current Flash memory. The model is supported by device structure analysis, experimental and simulation work

2:25 p.m.
34.3  A Novel Planar Floating-Gate (FG) / Charge-Trapping (CT) NAND Device Using BE-SONOS Inter-Poly Dielectric (IPD), H.-T. Lue, P.-Y. Du, T.-H. Hsu, Y.-H. Hsiao, S.-C. Lai, S.-Y. Wang, S.P. Hong, M.T. Wu, F.H. Hsu, N.Z. Lien, C.-P. Lu, J.-Y. Hsieh, L.-W. Yang, T. Yang, K.-C. Chen, K.-Y. Hsieh, R. Liu, C.-Y. Lu, Macronix International Co. Ltd.

We propose a completely new approach for NAND Flash scaling- a planar FG using a trapping IPD for storage. Our concept is to combine the merits of CT and FG – CT for good retention and scaling to few-electron regime and FG for edge effect immunity and faster erase. The planar “fusion� FG/CT devices are fabricated by replacing the conventional IPD ONO of a FG device by a CT BE-SONOS structure. Both simulation and experimental results indicate that most of the stored electrons are trapped inside the nitride instead of the FG. The CT storage provides excellent retention even for a very thin tunnel oxide (<5nm). On the other hand, the thin FG provides an equi-potential channel that screens any non-uniform injection effect.

2:50 p.m.
34.4  Reliability Improvement in Planar MONOS Cell for 20nm-node Multi-Level NAND Flash Memory and Beyond, W. Sakamoto, T. Yaegashi, T. Okamura, T. Toba, K. Komiya, K. Sakuma, Y. Matsunaga, Y. Ishibashi, H. Nagashima, M. Sugi, N. Kawada, M. Umemura, M. Kondo, T. Izumida, N. Aoki, T. Watanabe, Toshiba Corporation

20nm-node planar MONOS cell which has improved reliability is developed. Extremely wide program/erase Vth window and good retention characteristics after cycling stress are obtained by buried charge cell structure. The buried charge planar MONOS cell is suitable for Flash memory with 20nm-node and beyond.

3:15 p.m.
34.5  Potential Well Engineering by Partial Oxidation of TiN for High-Speed and Low-Voltage Flash Memory with Good 125°C Data Retention and Excellent Endurance, G. Zhang, C.H. Ra, H.-M. Li, C. Yang, W.J. Yoo, Sungkyunkwan University

Potential well engineering is proposed for NAND Flash memory. The engineered well (EW) has a variable tunnel barrier. It switches the P/E and retention modes by EW transformation, and it is insensitive to tunnel barrier degradation. It enables fast program (10E7).

3:40 p.m.
34.6  Understanding STI Edge Fringing Field Effect on the Scaling of Charge-Trapping (CT) NAND Flash and Modeling of Incremental Step Pulse Programming (ISPP), H.-T. Lue, T.-H. Hsu, Y.-H. Hsiao, S.-C. Lai, E.-K. Lai, S.P. Hong, M.T. Wu, F.H. Hsu, N.Z. Lien, C.-P. Lu, S.-Y. Wang, J.-Y. Hsieh, L.-W. Yang, T. Yang, K.-C. Chen, K.-Y. Hsieh, R. Liu, C.-Y. Lu, Macronix International Co. Ltd.

The impact of edge fringing field effect on charge-trapping (CT) NAND Flash with various STI structures is extensively studied for a thorough understanding. First, we find that the edge fringing field can cause abnormal subthreshold current during programming. Second, the edge fringing field effect significantly changes the P/E speed and degrades the incremental-step-pulse programming (ISPP) slope from ideal value (=1). By using 3D simulation we found that the edge fringing field greatly degrades the tunnel oxide electric field, and more charge injection is required to obtain the same memory window. We propose an analytical ISPP model and successfully simulate various STI structures.

4:05 p.m.
34.7  Program Charge Effect on Random Telegraph Noise Amplitude and Its Device Structural Dependence in SONOS Flash Memory, J.P. Chiu, Y.L. Chou, H.C. Ma, T. Wang, S.H. Ku*, N.K. Zou*, V. Chen*, W.P. Lu*, K.C. Chen*, C.-Y. Lu*, National Chiao-Tung University, *Macronix International Co. Ltd.

Nitride program charge effect on the amplitude of random telegraph noise in SONOS flash cells is investigated. We measure and simulate RTN amplitudes in floating gate flash, planar SONOS, and FinFET SONOS cells. We find that a planar SONOS has a wide spread in RTN amplitudes after programming due to a current-path percolation effect caused by random discrete nitride charges. The RTN amplitude spread can be significantly reduced in surrounding gate SONOS.