Session 9: Characterization, Reliability, and Yield

Session 9: Characterization, Reliability, and Yield - Memory Reliability Challenges

Tuesday, December 11, 9:00 a.m.
Continental Ballroom 1-3

Co-Chairs: Ya-Chin King, National Tsing Hua University
Satoru Yamada, Samsung Electronics Co., Ltd.

9:00 A.M.
Introduction

9:05 a.m.
9.1 Radically Extending the Cycling Endurance of Flash Memory (to > 100M Cycles) by Using Built-in Thermal Annealing to Self-heal the Stress-Induced Damage, H.-T. Lue, P.-Y. Du, C.-P. Chen, W.-C. Chen, C.-C. Hsieh, Y.-H. Hsiao, Y.-H. Shih, C.-Y. Lu, Macronix International Co. Ltd.

Flash memory endurance is limited by the tunnel oxide degradation after repeated P/E stressing in strong electric field. Thermal annealing should be able to repair the oxide damage but such theory cannot be tested in real time since completed device cannot endure high temperature > 400°C and long baking time is impractical for real time operation. In this work, we propose and demonstrate a novel self-healing Flash, where a locally high temperature (>800°C), short time (ms) annealing is generated by a built-in heater. By modifying the word line (WL) from a single-ended to a double-ended structure, the WL can carry a current to generate Joule heating; and the proximity of the gate can readily heat the tunnel oxide of the Flash device, annealing out the damage caused by P/E cycling. We discover that a BE-SONOS charge-trapping NAND Flash device can be quickly annealed within a few milliseconds. With this novel technique, we demonstrate a record-high endurance of >100M (10⁸) P/E cycles with excellent post-100M-cycle retention. Interestingly, the WL heater can be used to achieve faster erasing although normally FN tunneling should be temperature-independent. At the extreme temperature achieved in our heating-while-erasing experiments electron de-trapping from the charge trapping nitride, accompanying hole FN tunneling, also occurs, resulting in faster erasing. Finally, a novel design architecture for implementing the self-healing Flash memory is proposed.

9:30 a.m.
9.2 Quantitative and Predictive Model of Reading Current Variability in Deeply Scaled Vertical Poly-Si Channel for 3D Memories, M. Toledano-Luque, R. Degraeve, B. Kaczer, B. Tang*, P. Roussel, P. Weckx, J. Franco, A. Arreghini, A. Suhane, G.S. Kar, G. Van den bosch, G. Groeseneken, J. van Houdt,imec, *Liverpool John Moores University

3D vertical poly-Si channel SONOS devices are emerging as the most prominent alternative for the 10 nm nonvolatile memory technology node and beyond provided that a significant drive current I_READ is delivered at a fixed reading gate voltage V_READ. Recently, we showed the discrete drops observed in the transfer characteristic (I_D vs. V_G) of 3D transistors are linked to single electron trapping in the highly defective poly-Si channel [3]. This effect is in addition to low poly-Si mobility, resulting in the low drain current measured on poly-Si channel transistors. As an immediate consequence, a large drain current ID variability is observed in such deeply scaled devices. In order to develop a correct model to predict this ID variability, both the i) charging component and ii) the intrinsic g_m-variability have to be separately characterized and physically understood, to be afterwards correctly combined. The present abstract shows the methodology to predict the I_D distribution at fixed reading gate voltage V_READ by physical understanding of both effects: electron trapping and transconductance variations.

9:55 a.m.
9.3 Characterization of Traps in 3-D Stacked NAND Flash Memory Devices with Tube-Type Poly-Si Channel Structure, M.K. Jeong, S.M. Joe, B.S. Jo, H.J. Kang, J.H. Bae, K.R. Han*, E. Choi*, G. Cho*, S.K. Park*, B.G. Park, J.H. Lee, Seoul University, *SK Hynix Inc.

Trap density (D_it) was extracted for the first time in 3-D stacked NAND flash memory with a tube-type poly-Si channel structure. We verified extracted Dit with conductance method and charge pumping method in 32 nm floating gate (FG) NAND flash memory. In 3-D stacked NAND flash memory device, the Dit extracted by conductance method was 1~2×10¹²/(cm^-2eV^-1) in E_C-E_T of 0.15~0.35 eV. The simulation results of I_BL-V_CG and C-V_CG based on the D_it were conformable with the measurement data. Then we investigated effects of program/erase (P/E) cycling on 1/f noise in NAND flash devices. Finally, we extracted firstly the position of a trap generating random telegraph noise (RTN) by considering cylindrical coordinate and pass cell resistance in the 3-D stacked NAND flash memory cell.

10:20 a.m.
9.4 Device Considerations for High Density and Highly Reliable 3D NAND Flash Cell in Near Future (Invited), S.-K. Park, SK Hynix Inc.

Highly manufacturable and reliable 3D NAND flash cell intended to minimize both stack height and word-line resistance has been suggested. The key cell characteristics such as cell Vth distribution, disturbance, and reliability are compared with our FG cell of 2y node in chip level, and several future challenges for 3D era will be addressed.

10:45 a.m.
9.5 RRAM SET Speed-Disturb Dilemma and Rapid Statistical Prediction Methodology, W.-C. Luo, J.-C. Liu, H.-T. Feng, Y.-C. Lin, J.-J. Huang, K.-L. Lin, T.-H. Hou, National Chiao Tung University

This paper presents a first comprehensive study of SET speed-disturb dilemma in RRAM using statistically-based prediction methodologies. A rapid ramped-voltage stress based on percolation model and power-law V-t dependence showed excellent agreement with the time-consuming constant-voltage stress, and was applied to evaluate current status of RRAM devices in the literature.

11:10 a.m.
9.6 Methodology for the Statistical Evaluation of the Effect of Random Telegraph Noise (RTN) on RRAM Characteristics, D. Veksler, G. Bersuker, B. Chakrabarti*, E. Vogel*, S. Deora, D.C. Gilmer, H.-F. Li**, S. Gausepohl**, P.D. KirschSEMATECH, *University of Texas, Dallas, **College of Nanoscale Science and Engineering

We introduce a figure of merit (FoM) to quantify RRAM read current instability, a complex multi-level RTN-like signal, generally observed in read current. Log(FoM) follows a normal statistical distribution describing the probability of occurrence of a read current fluctuation of a given amplitude. The developed statistical model for the read current instability is significant because it allows to estimate the maximum size and minimum operating current for a high density RRAM array.

11:35 a.m.
9.7 A 32nm SRAM Reliability Macro for Recovery Free Evaluation of NBTI and PBTI, P. Jain, A. Paul, X. Wang, C. Kim, University of Minnesota

A scalable test structure for recovery free evaluation of the impact of NBTI and PBTI on read/write operation in a SRAM macro has been developed. A novel non-invasive methodology keeps the stress interrupts for measurements within a few microseconds, preventing unwanted BTI recovery, while providing a parallel stress-measure capability on 32kb sub-arrays. Measurement results in a 32nm high-?/metal-gate silicon-on-insulator process show that proposed schemes provides 35mV better accuracy in read VMIN and over 10X accuracy in BFR.