Session 9: Characterization, Reliability, and Yield - Memory Reliability Challenges
Tuesday, December 11, 9:00 a.m.
Co-Chairs: Ya-Chin King, National Tsing Hua University Satoru Yamada, Samsung Electronics Co., Ltd.
Flash memory endurance is limited by the tunnel oxide degradation after repeated P/E stressing in strong electric field. Thermal annealing should be able to repair the oxide damage but such theory cannot be tested in real time since completed device cannot endure high temperature > 400°C and long baking time is impractical for real time operation. In this work, we propose and demonstrate a novel self-healing Flash, where a locally high temperature (>800°C), short time (ms) annealing is generated by a built-in heater. By modifying the word line (WL) from a single-ended to a double-ended structure, the WL can carry a current to generate Joule heating; and the proximity of the gate can readily heat the tunnel oxide of the Flash device, annealing out the damage caused by P/E cycling. We discover that a BE-SONOS charge-trapping NAND Flash device can be quickly annealed within a few milliseconds. With this novel technique, we demonstrate a record-high endurance of >100M (108) P/E cycles with excellent post-100M-cycle retention. Interestingly, the WL heater can be used to achieve faster erasing although normally FN tunneling should be temperature-independent. At the extreme temperature achieved in our heating-while-erasing experiments electron de-trapping from the charge trapping nitride, accompanying hole FN tunneling, also occurs, resulting in faster erasing. Finally, a novel design architecture for implementing the self-healing Flash memory is proposed.
3D vertical poly-Si channel SONOS devices are emerging as the most prominent alternative for the 10 nm nonvolatile memory technology node and beyond provided that a significant drive current IREAD is delivered at a fixed reading gate voltage VREAD. Recently, we showed the discrete drops observed in the transfer characteristic (ID vs. VG) of 3D transistors are linked to single electron trapping in the highly defective poly-Si channel . This effect is in addition to low poly-Si mobility, resulting in the low drain current measured on poly-Si channel transistors. As an immediate consequence, a large drain current ID variability is observed in such deeply scaled devices. In order to develop a correct model to predict this ID variability, both the i) charging component and ii) the intrinsic gm-variability have to be separately characterized and physically understood, to be afterwards correctly combined. The present abstract shows the methodology to predict the ID distribution at fixed reading gate voltage VREAD by physical understanding of both effects: electron trapping and transconductance variations.
Trap density (Dit) was extracted for the first time in 3-D stacked NAND flash memory with a tube-type poly-Si channel structure. We verified extracted Dit with conductance method and charge pumping method in 32 nm floating gate (FG) NAND flash memory. In 3-D stacked NAND flash memory device, the Dit extracted by conductance method was 1~2×1012/(cm-2eV-1) in EC-ET of 0.15~0.35 eV. The simulation results of IBL-VCG and C-VCG based on the Dit were conformable with the measurement data. Then we investigated effects of program/erase (P/E) cycling on 1/f noise in NAND flash devices. Finally, we extracted firstly the position of a trap generating random telegraph noise (RTN) by considering cylindrical coordinate and pass cell resistance in the 3-D stacked NAND flash memory cell.
Highly manufacturable and reliable 3D NAND flash cell intended to minimize both stack height and word-line resistance has been suggested. The key cell characteristics such as cell Vth distribution, disturbance, and reliability are compared with our FG cell of 2y node in chip level, and several future challenges for 3D era will be addressed.
This paper presents a first comprehensive study of SET speed-disturb dilemma in RRAM using statistically-based prediction methodologies. A rapid ramped-voltage stress based on percolation model and power-law V-t dependence showed excellent agreement with the time-consuming constant-voltage stress, and was applied to evaluate current status of RRAM devices in the literature.
We introduce a figure of merit (FoM) to quantify RRAM read current instability, a complex multi-level RTN-like signal, generally observed in read current. Log(FoM) follows a normal statistical distribution describing the probability of occurrence of a read current fluctuation of a given amplitude. The developed statistical model for the read current instability is significant because it allows to estimate the maximum size and minimum operating current for a high density RRAM array.
A scalable test structure for recovery free evaluation of the impact of NBTI and PBTI on read/write operation in a SRAM macro has been developed. A novel non-invasive methodology keeps the stress interrupts for measurements within a few microseconds, preventing unwanted BTI recovery, while providing a parallel stress-measure capability on 32kb sub-arrays. Measurement results in a 32nm high-?/metal-gate silicon-on-insulator process show that proposed schemes provides 35mV better accuracy in read VMIN and over 10X accuracy in BFR.