2005 IEDM Short Courses

Low Power "System On Chip" CMOS Technology Platforms
Next Generation Semiconductor Manufacturing

Sunday, December 4, 9:00 a.m. — 5:30 p.m.
International Ballroom Center

Low Power technologies serve the rapidly growing portable electronics market including laptop computers, PDAs, cell phones, WLAN/WPAN connectivity devices, MP3 players, etc. A wide range of semiconductor technologies and design techniques serve this market. This short course will focus on CMOS SoC technology platform technologies and design techniques essential for enabling this market segment.

The short course is organized to focus on three areas: technology, design and modeling. The first lecture will discuss the requirements and transistor design issues in current and future low power technologies. The course will focus on issues and tradeoffs between low standby and low active power device design and will conclude with requirements for future innovations in low power process and transistor design. The second lecture will discuss embedded memory technologies critical for low power systems. Challenges and technology requirements as well as trends in embedded SRAM, DRAM, NV memory and emerging memory technologies will be discussed. The third and fourth lecture will cover digital and analog/RF circuit design aspects with special emphasis on technology and circuit co-optimization for low power systems using nanometer CMOS technologies. The digital design section will discuss general challenges for low power technology, discuss in detail circuits for leakage avoidance, control and tolerance, low power architectures and various system power management concern and conclude with discussion on technology, circuits, architecture and system co-optimization. The lecture on analog/RF designs will cover the impact of scaled CMOS on key design Figures-of-Merit, followed by discussion on specific analog/RF design blocks and the challenges for technology and design co-optimization for designs such as Op-Amps, converters, LNAs and VCOs. The final lecture will focus on modeling of scaled CMOS with emphasis on the modeling aspects critical for low power systems. Reduced supply voltages and the push to operate at low currents mean that the accuracy of near- and below-threshold modeling for MOSFETs is of prime importance, yet this is precisely where many existing models have the least physical accuracy. Modern surface-potential based models are recognized as the most physical and accurate near threshold, and will be reviewed in detail. Other critical near threshold modeling aspects including variability, noise and leakage current will also be discussed. Through this series of lectures, a comprehensive overview of state of the art Low Power SoC CMOS platforms will be provided.

Process Technology

Instructor: Scott Crowder, IBM

What is a Low Power Process?
     Low Standby vs. Low Active Power
     Low Cost vs. High Performance
Transistor Design for Low Standby Power
     Standby Power Components
     Scaling Challenges
     Methods for Parasitic Leakage Reduction
     Materials/Innovations for Performance Scaling
Transistor Design for Low Operating Power
     Operating Power Components
     Scaling Challenges
     Mobility Engineering
     Materials/Innovations for Performance Scaling
Additional Requirements for Low Power "System On Chip" Technology
     BEOL Scaling
     Passive Elements

Embedded Memory Technology for Low Power Systems

Instructor: Yasushi Yamagata, NEC Electronics

Importance of Embedded Memory
     Memory Content Trend
     Single-Core to Multi-Core
SRAM Challenges with Device Scaling
     Low Voltage Operation
     Device Variability
     Leakages
     SER
     Solution Candidate
Embedded DRAM
     Advantage/Requirement of Embedded DRAM
     Technology Trend
     Trench vs. Stack
     Embedded DRAM Application
Embedded NV Memory
     Advantage/Requirement of Embedded NV
     Technology Trend
     Floating Gate vs. Charge Trap
     Embedded Flash for ROM Replacement
Emerging Memory Technology
     Overview of Various Technologies — Performance Trade-offs
     MRAM Technology - Issues and Future Prospects
     Nano-Bridges

Digital Design for Low Power Systems

Instructor: Shekhar Borkar, Intel

Active and Leakage Power Challenges
     Technology Outlook
     Active and Leakage Power Projections
     Cost
Circuits for Leakage Avoidance, Control, and Tolerance
     Dual Vt, Body Bias, Stack Effect, and Sleep Transistor Techniques
     Leakage Tolerant High Performance Circuits
     Leakage Control for Memory Circuits
Microarchitectures for Low Power
     Optimum Logic Pipelines
     Throughput Oriented Designs
     Multi-Everywhere: From Threads To Cores
     Technology and Design Co-Optimization Challenges
System Power Management
     Fine Grain Power Management
     Power Delivery
     Low Power Platform Design
     Power Management Software
Technology, Circuits, Microarchitecture, and System Co-Optimization

Analog/RF Design in Nanometer CMOS Technologies

Instructor: Willy Sansen, KU Leuven

Impact of Nanometer Channel Lengths on Transistor Performance
     Intrinsic Gain Reduction
     Speed Enhancement
     Noise - Thermal and 1/f Noise
     Offset
     Distortion Cancellation
Operational Amplifiers with Supply Voltage Below 1 V and with Minimum Power Consumption
     Gate-Driven, Bulk-Driven
     Single-Stage Amplifiers
     Two-Stage Miller Op-Amps
     Multi-Stage Amplifiers
     Technology and Design Co-Optimization Challenges
Low-Voltage Low-Power Delta-Sigma A-to-D Converters
     Switched Op-Amp Approach
     Full-Feedforward Approach
     Input-Series-Resistor Approach
     Technology and Design Co-Optimization Challenges
Communication Circuits
     VCO's with Low Phase Noise
     LNA's with Low Noise Figure
     Technology and Design Co-Optimization Challenges

Modeling for Digital and AMS/RF Design

Instructor: Colin McAndrew, Freescale Semiconductor

Overview
     Modeling Challenges and needs for Low-Power
     Additional Challenges from Technology Scaling
     Digital and Analog Needs
     Linkage to Circuit and System Level Design and Simulation
MOSFET Modeling
     Accurate Near-Threshold Modeling, State-of-the-Art Surface Potential Models
     Variability Exacerbation from Technology Scaling and Low Power Operation
     Noise
     Proximity Effects
Passive and Parasitic Modeling
     Shift in the Nature of Parasitic Capacitances, Dependence on Adjacent Structures
     Difficulties in Modeling of and Importance of Leakage for Static Power
System Level Modeling
     System and Architecture Level Modeling and Optimization for Low Power Design
     Dynamic and Static Power Dissipation

Sunday, December 4, 9:00 a.m. — 5:30 p.m.
International Ballroom East

Course Organizer: C. Rinn Cleavelin, Texas Instruments

The last 2-3 generations of semiconductor manufacturing have presented some unique challenges. As the traditional scaling laws have started to slow, new materials have been increasingly added in order to continue the consistent gains in performance. These new materials have placed new requirements beyond just the typical scaling of feature sizes. Additionally the varieties of end-user requirements for ICs have led to a proliferation of processes tailored to the features of the application. These shifts have led to a need for substantial innovation in order to enable manufacturing of multi-core, multi-GHz microprocessors, multi-Gb memories, and low power SoCs. Frequently in the same factory! This short course will examine the requirements for the processes, from FEOL and BEOL to packaging to yield and reliability, that will be needed in order to produce these chips at high performance, high density and low cost. Through the five lectures, the speakers will detail the state of the art in process technology, the trends in development and provide insight into what the next generation of semiconductor manufacturing will look like.

The first lecture consists of an overview of the state of semiconductor manufacturing and what the future holds. This includes the global business trends, the impacts of introducing new materials and novel device architectures, and the outlook for 450mm wafers. The second lecture focuses on the front end manufacturing technology, delving into the problems confronting the development of new substrates, strain techniques, scaled junctions and the anticipated changes to the gate stack. In the third lecture, the speaker will detail the challenges in the back end manufacturing technology, including the material options for the interlayer dielectrics and interconnect metals, the integration issues with introducing these materials and examining the overall strategy for development. With the variety of chip packages and the tight coupling of the BEOL processing and the package, the fourth lecture will focus on packaging. The speaker will cover the state of lead-free, Cu, Low-k packaging and the obstacles in development of next generation packages including heat dissipation, SoC and interconnect options. The final lecture will focus on the impacts of these new materials/structures on the yield and reliability of the dies. The speaker will address the inevitable new fail modes that will require innovation in testing, models, tools and solutions to enable high yield and reliable chips.

Introduction

Organizer: C. Rinn Cleavelin, Texas Instruments

Overview of the Next Generation of Semiconductor Manufacturing

Instructor: Jai Hakhu, Intel

     Worldwide Semiconductor Business Trends at the 45nm Node and Beyond
     New Technology Challenges
     Key Areas for Manufacturing Concern
     Manufacturing Headlights — where are we headed?
     Outlook for 450mm wafers
     Summary

Front End of Line Manufacturing Technology

Instructor: Raj Jammy, IBM/SEMATECH

Brief Review of current generation
Scaling trends: factors driving change
     Power and performance
Substrates
     Ultra Thin Body SOI
     sSOI/SGOI
     Hybrid Orientation Technology (HOT)
Gate Dielectrics
     Scaled SiON
     High k dielectrics
Gate Electrodes
     Doped poly-Si
     Metal Gates
Junctions
     Scaling considerations and impact of series resistance
     Rapid thermal anneals vs mSec anneal technologies
Strain Engineering
     Uniaxial vs biaxial
     SiGe and stress liners
Likely elements for next generation CMOS
Next generation low power technologies
Issues in implementation of key elements
     Integration challenges
     Process development and control
     Contamination concerns
     Reliability concerns
Manufacturability concerns
     Tool maturity/availability
     Process control
     CoO
     Metrology
     Operational flexibility and agility
Summary and outlook for future scalability and manufacturability

Back End of Line Manufacturing Technology

Instructor: Hans-Joachim Barth, Infineon

Scope
Interconnect Scaling Directions
     Interconnect hierarchy
Materials and Processes
     overview established materials & processes (180nm-65nm node)
     Low k materials
     Thermo-mechanical properties & stress (oxide, dense & porous-low k)
     development of CVD low k precursors (3MS _ cyclic)
     Barriers & Cu seed
     ionized-PVD (pre-clean, re-sputtering approaches)
     ALD-barriers
     Cu – seed/plating/CMP
Integration Challenges
     Dual damascene integration
     Etch, ash & clean
     Barrier / low k interaction
     Adhesion & moisture control
Manufacturing and Tool Strategy
     Tool strategy & costs
     New metrology challenges
     Advanced process control strategy
     Frontside & backside cleans
     Wafer edge control
Future Interconnect Strategy
     limitations of material innovations
     design options
     evolutional approach (e.g. airgaps, 3D-IC stacking)
     future connectivity (e.g. RF & optical on chip, nanotubes)
Conclusions and future outlook

Packaging & the Integration with BEOL Manufacturing

Instructor: TBD

Materials — Lead Free, What's after Cu/Low-k
Packaging Challenges — Heat Dissipation, Stress, 3D Interconnect, Chip Resistivity
Manufacturing — Package Configurations (FLIP, SIP, etc), BEOL Interface, WLCSP
Future of Packaging — Roadmap Requirements, Optical Interfaces, MEMs, RFID
Summary

Reliability & Yield

Instructor: Joe McPherson, Texas Instruments

Outline for presentation

General scaling trends impacting reliability & yield

New materials integration with conventional scaling
     Ultra-thin SiO_xN_y gate-dielectric scaling
     High-k gate dielectrics
     Metal Gates
      Low-k interconnect dielectrics

Old materials integration with novel structures
     Strained Silicon
     Cladded Cu
     Non-planar devices

Defect Detection
     Wafer-level Monitoring — diminishing returns
     Physical Failure Analysis — diminishing returns
     Electrical Failure Analysis — defect modeling required
     Defect test structures — physics-based defect structures required

Major reliability challenges for continued CMOS scaling
     Stress migration
     Electromigration
     Interconnect Cracks and Delamination
     Low-k TDDB
     Ultra-thin SiOxNy TDDB
     High-k TDDB
     NBTI
     Plasma Charging
     Thermo-Mechanical Failures
     Soft-Errors
     ESD
     Power Dissipation
     Design-In Reliability
     Build-in Reliability

SoC Challenges
     Power density
     Stacked Die

Beyond CMOS
     Reinventing CMOS
     "Nanoelectronics"
     Molecular Electronics

©2005 by the IEEE http://www.ieee.org