Call For Papers

The twelfth annual IITC is sponsored by the IEEE Electron Devices Society and the Japan Society of Applied Physics as a premier conference for interconnect technology. The IITC provides a forum for professionals and researchers in semiconductor processing, advanced materials, equipment development, and interconnect systems to present and discuss exciting new science and technology. Contributions from universities, national laboratories, IDMs, foundries, and equipment and materials suppliers are encouraged.

CONFERENCE FORMAT:

Technical Papers: Contributed papers addressing all aspects of interconnect technology will be rigorously reviewed. Papers will be selected for either oral or poster presentation.

• Regular papers, with 3-page abstracts will be selected for either oral or poster presentation. The Organizing Committee explicitly solicits contributions for new areas: 3D, memory, manufacturing, packaging and new materials/concepts.
• In addition, papers with 2-page abstracts will be selected for a special poster session for New Engineers and Students.

Exhibits/Seminars: New products, processes, analytical methods and materials will be exhibited at the conference on June 1 and 2. Supplier seminars will be held on the 1^st and/or 2^nd evenings of the conference. Please contact the Conference Headquarters for details.

Short Course: A one-day short course on leading edge interconnect technology will be offered on Sunday, May 31, 2009.

SUBMISSION OF PAPERS:

Deadline: January 19, 2009

NOTE Submission of an abstract for review and subsequent acceptance is considered by the commitee as an agreement that the work will not be placed in the public domain by the author prior to the conference. Accepted papers or significant portions of the work may not be placed in the public domain prior to the conference. Violation will be grounds for automatic withdrawal of the paper by the conference committee. Inclusion of materials from publications by other authors may be done only with their expressed permission and with a citation associated with the reproduced material. Approriate company or government clearance must be obtained by the authors before submission and an IEEE Copyright Form will be required. Submitted papers will not be returned to the authors.

Oral presentations will be 20 minutes in length followed by a 5 minute question period. Poster authors will be required to be at their presentations for a 2-hour period on the day of their poster display.

Papers must be submitted electronically (SUBMIT PAPER). Do not email or mail hard copies to the conference office. Please read the paper preparation and submission guidelines before preparing your paper. In order for your paper to receive a full review, the following information MUST be entered on the website along with your submission:

• Title of paper
• First author name with complete mailing address, phone, fax and email address
• Names, affiliations, city state or country of additional authors
• Person to whom correspondence should be sent, if other than the first author
• Identification as invited or student paper
• Suggestions for up to three potential conference sessions for the paper. See Subjects of Interest

ACCEPTED PAPERS WILL BE PRINTED IN THE PROCEEDINGS WITHOUT THE OPPORTUNITY FOR FURTHER CHANGE. Paper length inclusive of all illustrations, charts and tables must be 3 pages for regular oral/poster sessions, and 2 pages for special poster sessions for New Engineers and Students, respectively. Contact information for each author must be listed on the first page of the paper: name, affiliation, city, state or country. Authors of accepted papers will be notified by March 2, 2009.

Note: Accepted papers may be used for publicity purposes and portions of these papers may be quoted in pre-conference magazine articles and also via the Web. If this is NOT acceptable, authors must indicate this on the Paper Submission site when submitting the paper for review.

SUBJECTS OF INTEREST and PRELIMINARY SESSION TITLES:

Materials and Unit Processes

• Dielectric materials (low k, high k, ARCs, etc.) and associated deposition processes (vapor deposition, CVD, spin-on, etc.)
• Metal deposition processes/equipment (PVD, CVD, ALD, electroplating, etc.) planarization processes for dielectrics and metals, equipment and metrology issues. Alternative planarization techniques
• Interconnect specific patterning processes (lithography, etch, etc.) including wet/dry strip and cleaning
• Novel or improved tools for metrology and characterization applicable to interconect

Process Integration for Logic or Memory and Interconnect Systems:

• Multilevel interconnect processes, clustered processes, novel interconnect structures, contact/via integration, metal barrier and materials interface issues, etc.
• Integration processes and issues specific to logic or memory
• RF and high frequency passive components
• Interconnect performance modeling and high frequency characterization
• Interconnect system integration, novel architectures and advanced interconnect concepts (optical, superconductors, etc.)
• Across-generation manufacutring science

Process Control/Modeling for Manufacturing

• CMP, metal/dielectric deposition and etching processes, PVD, CVD, electroplating, etc.
• Across-generation manufacturing science

Reliability

• Metal electromigration and stress voiding, dielectric integrity and mechanical stability, thermal effects, passivation issues, interconnect reliability prediction/modeling.

TSV and 3D Integration

• Materials, process integration, 3D with memory, reliability

Packaging

• Chip-package interaction, thermal management technology
• Green technology (Sn-based solder, Cu-pillar, etc.)
• Flip-chip, wafer level packaging, chip-on-chip, MCM, etc.
• Novel board level interconnect, package architectures

Novel Materials and Concepts

• Advanced interconnect concepts, optical interconnect, superconductors
• carbon nanotubes, nanowires, nano materials
• Novel non-volatile, interconnect embedded memories (PCM, resistive, etc.)
• Interconnects for display and flexible devices
• Interconnect/metallization issues on MEMs and bio devices

SUBMIT YOUR PAPER

LATE NEWS PAPERS:

Deadline: April 11, 2008

A very limited number of papers reporting the latest breakthroughs may be accepted as late news papers. Prospective authors should email (iitc@his.com) a pdf file (REMEMBER to "embed all fonts") of the paper. The paper must be two pages in length inclusive of illustrations, charts and tables. Paper format must adhere to the guidelines described in the Author's Kit. Accepted late news papers will be presented orally for 10 minutes followed by a 5 minute question period. Late news papers will be printed in the conference proceedings but will not be included in the advance program. An IEEE copyright form will be required.

GENERAL INFORMATION:

For additional information, including Author's Kits, Supplier/Exhibit Information, Registration/Hotel Information, please contact:

IITC c/o Widerkehr & Associates, 19803 Laurel Valley Place, Montgomery Village, MD 20886 USA, Tel. +1-301-527-0900 x104, Fax. +1-301-527-0994, Email: iitc@his.com

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