2008 Technical Program

Monday, June 2

SESSION 1: PLENARY

8:30
Welcome
Co-Chairs: Gary W. Ray, Intel Corp.
Kuniko Kikuta, NEC Electronics Corp.
Ivo Raaijmakers, ASM International nv

1.1 Keynote Presentation - Zero Defect – Reliability for Automotive Electronics,
Dr. Valentin von Tils, Vice President, ASIC Platform Development

9:30
Break in the Exhibit Hall

SESSION 2: 3-D SILICON
Co-Chairs: Mike Shapiro, IBM and Young-Chang Joo, Seoul National University

10:00
2.1 INVITED: Through Silicon Via Tech-nologies for Extreme Miniaturized 3D integrated Wireless Sensor Systems,
P. Ramm, Fraunhofer Institute, Dresden, Germany

10:25
2.2 INVITED: Three-Dimensional Integration Technology Using Self-Assembly Technique and Super Chip Integration,
M. Koyanagi, Tohoku University, Sendai, Japan

10:50
2.3 A 3D-IC Technology with Integrated Microchannel Cooling,
D. Sekar, C. King, B. Dang*, T. Spencer, H. Thacker**, P. Joseph, M. Bakir, and J. Meindl, Georgia Institute of Technology, Atlanta, GA, *IBM Research and **Nanonexus, Inc.

11:15
2.4 Extraction of the Appropriate Material Property for Realistic Modeling of Through-Silicon-Vias using µ-Raman Spectroscopy,
C. Okoro, Y. Yang, B. Vandevelde, B. Swinnen, D. Vandepitte*, B. Verlinden*, and I. De Wolf, IMEC and *Katholieke Universiteit, Leuven, Belgium

11:40
2.5 Resistance to Electromigration of Purely Intermetallic Micro-Bump Interconnections for 3D-Device Stacking,
R. Labie, W. Ruythooren, K. Baert, E. Beyne, and B. Swinnen, IMEC, Leuven, Belgium

12:05
LUNCH

SESSION 3: POSTER I 1:00- 3:00
Exhibit Hall

3.1 High Performance Cu Containing Ru or RuNX for Barrierless Metallization,
J.P. Chu and C.H. Lin*, National Taiwan University of Science and Technology, Taipei, Taiwan and *Chin-Min Institute of Technology, Tou-Fen, Taiwan

3.2 Development and Optimization of Porous pSiCOH Interconnect Dielectrics for 45 nm and Beyond,
A. Grill, S. Gates, C. Dimitrakopoulos, V. Pagel, S. Cohen, Y. Ostrovski, E. Liniger, E. Simonyi, D. Restaino* S. Sankaran*, S. Reiter**, A. Demos**, K.S. Yim**, V. Nguyen**, J. Rocha**, and D. Ho**, IBM – TJ Watson Research Center, Yorktown Heights, NY, *IBM Semiconductor Research & Development Center, Hopewell Junction, NY and **Applied Materials, Santa Clara, CA

3.3 Mechanistic Study of CO₂ Plasma Damage to OSG Low k Dielectrics,
H. Shi, J. Bao, H. Huang, B. Chao, S. Smith, Y. Sun, P.S. Ho, A. Li*, M. Armacost*, and D. Kyser*, University of Texas, Austin, TX and *Applied Materials, Sunnyvale, CA

3.4 A Self-Aligned Air Gap Interconnect Process,
H-W. Chen, S-P. Jeng, H-Y. Tsai, Y-W. Liu, CH. Yu and YC. Sun, Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan

3.5 Production Worthy 3D Interconnect Technology,
H.J. Tu, W.J. Wu, J.C. Hu, K.F Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan. Yang, H.B. Chang, W.C. Chiou, and C.H. Yu, Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, Taiwan

3.6 3D IC Process Integration Challenges and Solutions,
K. Powell, S. Burgess, T. Wilby, R. Hundman, and J. Callahan*, Aviza Technology, Newport, UK and *Cubic Wafer, Merrimack, NH

3.7 Current-carrying Capacity of Carbon Nanofiber Interconnects,
H. Kitsuki, T. Saito, T. Yamada, D. Fabris, J.R. Jameson, P. Wilhite, M. Suzuki, and C.Y. Yang, Santa Clara University, Santa Clara, CA

3.8 3D Die-to-wafer Cu/Sn Microconnects formed simultaneously with an Adhesive Dielectric Bond using Thermal Compression Bonding,
S. Pozder, A. Jain, R. Chatterjee, Z. Huang, R.E. Jones, E. Acosta, B. Marlin*, G. Hillmann**, M. Sobczak^, G. Kreindl^^, S. Kanagavel^, H. Kostner**, and S. Pargfrieder^^, Freescale Semiconductor, Inc., Austin, TX, *Freescale Semiconductor, Inc., Chandler, AZ, **Datacon Technology GmBH, Radfeld, Austria, ^Cookson Electronics Semiconductor Products, Suwanee, GA and ^^EV Group, Scharding, Austria

3.9 Voltage Ramp and Time-Dependent Dielectric Breakdown in Ultra-Narrow Cu/SiO2 Interconnects,
H. Park, H.-B. Lee, H.-K. Jung, Z.-S. Choi, J.-Y. Bae, J.-W. Hong, K.-I. Choi, B.-L. Park, E.-J. Lee, J.-W. Kim, J.-M. Lee, G.-H. Choi, and J.-T. Moon, Samsung Electronics Co., Ltd., Korea

3.10 Key Factors to Sustain the Extension of a MHM-based Integration Scheme to Medium and High Porosity PECVD Low-k Materials,
Y. Travaly, J. Van Aelst, V. Truffert, P. Verdonck, T. Dupont, E. Camerotto, O. Richard, H. Bender, C. Kroes, D. De Roest*, G. Vereecke, M. Claes, Q.T. Le, E. Kesters, M. Van Cauwenberghe*, J. Beynet*, S. Kaneko**, H. Struyf, M. Baklanov, K. Matsushita**, N. Kobayashi**, H. Sprey*, and G. Beyer, IMEC, Leuven, Belgium, *ASM Belgium, Leuven, Belgium, **ASM Japan, Tokyo, Japan

3.11 Highly Reliable Low Resistance Cu Contact using Novel CVD Ru/TiN/Ti Stacked Liner,
M. Kitamura, K. Nomura, H. Matsumori, T. Watanabe, H. Matsuyama, J.H. Wada, T. Usui, and M. Hasunuma, Toshiba Corporation, Tokyo, Japan

3.12 Analytical Study of Leakage Characteristics Change during Multilevel Interconnect Process using Porogen-type Porous SiOC (k=2.4)/Cu System,
N. Ohashi, J. Nakahira, E. Soda, K. Tomioka, S. Chikaki, N. Oda, S. Kondo, and S. Saito, Semiconductor Leading Edge Technologies, Inc., Ibaraki, Japan

3.13 Copper Direct Bonding for 3D Integration,
P. Gueguen, L. Di Cioccio, M. Rivoire*, D. Scevola, M. Zussy, Charvet, L. Bally, D. Lafond, and L. Clavelier, CEA Leti – MINATEC, Grenoble, France and * STMicroelectronics, Crolles, France

SESSION 4: MATERIALS AND PROCESSING I
Co-Chairs: Ivo Raijimakers, ASM International and Kuniko Kikuta, NEC Electronics

3:00
4.1 INVITED: Process Control and Physical Failure Analysis for Sub-100nm Cu/Low-k Structrures,
E. Zschech, AMD Saxony LLC and Co., KG, Dresden, Germany

3:25
4.2 INVITED: Lithography Options and Challenges for Sub-45nm Node Interconnect Layers,
M. Maenhoudt, IMEC, Leuven, Belgium

3:50
4.3 Structure-Designable Formation-Method of Super Low-k SiOC Film (k=2.2) by Neutral-Beam-Enhanced-CVD,
S. Yasuhara, J. Chung, K. Tajima*, H. Yano*, S. Kadomura*, M. Yoshimaru*, N. Matsunaga*, T. Kuybota, H. Ohtake, and S. Samukawa, Tohoku University, Sendai, Japan and *Semiconductor Technology Academic Research Center (STARC), Yokohama, Japan

4:15
4.4 Micro Beam IR Characterization of Narrow Width (-100 nm) Low-k Spaces Between Cu Lines with Valence EELS Evaluation,
S. Ogawa, H. Seki*, Y. Otsuka*, S. Nakao, Y. Takigawa, and H. Hashimoto*, Semiconductor Leading Edge Technologies, Inc., Ibaraki, Japan and *Toray Research Center, Shiga, Japan

4:40
4.5 On the Elements of High Throughput Cu-CMP Slurries Compatible with Low Step Heights,
T, Kanki, T. Shirasu*, S. Takesako*, M. Sakamoto*, A.A. Asneil*, N. Idani*, T. Kimura, T. Nakamura, and M. Miyajima*, Fujitsu Laboratories Ltd., Tokyo, Japan and *Fujitsu Ltd., Mie and Tokyo, Japan

5:05
4.6 Hybrid e-CMP/CMP Process with Non-Contact Electrode Pad,
S. Kondo, D. Abe*, T. Enomoto*, S. Tominaga*, K. Yamada, and S. Saito, Semiconductor Leading Edge Technologies, Inc. Ibaraki, Japan and *Roki Techno Co., Ltd., Tokyo, Japan

5:30
SUPPLIER SEMINARS

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