8:30

COPPER INTERCONNECT TECHNOLOGY FOR 22 NM AND BEYOND
Jeff Gambino, IBM

This tutorial will provide an overview of advanced interconnect technologies, including dielectric materials, patterning, metallization, CMP, and packaging. New processes will be discussed, such as ultra-low K dielectrics, air-gap structures, refractory metal capping layers and low-damage resist strip and CMP methods. The effect of these processes on performance and reliability will be briefly described.

9:30

IMPACT OF INTERCONNECT VARIATIONS ON SYSTEM-ON-CHIP DESIGNS
Nagaraj NS, Texas Instruments, Inc.

Impact of manufacturing process variations on System-on-Chip (SoC) designs is becoming increasingly important in technology scaling. This tutorial covers the sources of interconnect variations and how they affect electrical performance and power in SoC designs in 65 nm and 45 nm technologies. Using the concept of circuit sensitivities, the impact of systematic variations in metal width and thickness due to etch and CMP effects are shown on typical SoC scenarios. Analysis on clock skew and race conditions are used to illustrate the different aspects of interconnect variations. Impact of random interconnect variations on circuit delay and power is presented and compared with the impact due to transistor device process variations.

10:30

BREAK

11:00

NANO-MATERIALS (SI NANOWIRE, CARBON, NANOTUBES, GRAPHENE): GROWTH, MATERIAL PROPERTIES AND APPLICATIONS IN NANO-ELECTRONIC
Vincent Jousseaume, CEA-LETI

With current microelectronic, approaching its scaling limit, a new emphasis has been placed on looking for new materials that can provide new or improved electronic properties. For instance, device technologies based on silicon nanowires (SiNW) and carbon nanotubes (CNT), structures that are just a few nanometers, promise orders of magnitude higher densities than CMOS.

This tutorial will discuss the use of nano-materials such as CNT, SiNW and graphene in global nano-electronics applications. A special attention will be brought to the use of these nano-materials for the realization of advanced interconnects. The different growth and fabrication technologies compatibles with CMOS applications will be described and the physical properties of these nano-objects will be discussed especially electronic properties mainly related to their dimensionality. Challenges in integration of these materials and device fabrication will be highlighted and an outlook on nano-materials based technology will be presented.

12:00

LUNCH

1:00

EMERGING NON-VOLATILE MEMORIES: NEW CHALLENGES FOR THE BEOL
Agostino Pirovano, STMicroelectronics

For more than ten years Flash memory technology has been able to follow the evolution of the semiconductor roadmap, becoming the non-volatile memory (NVM) market mainstream. Although it is expected that Flash will continue to scale with the same trend for next technology nodes, there are physical limitations to be faced and the downscaling beyond 32 nm generation is still considered critical. In this scenario several emerging NVM concepts are trying to exploit their performance advantages and better scaling capabilities to enter in the actual Flash-centric memory market. However all these alternative NVM concepts present new challenges related to the integration of novel materials in the CMOS BEOL. Aim of this tutorial is to present an overview of the emerging NVM concepts, their properties and potentialities, the compatibility challenges with the BEOL process and the issues that they must still face to eventually become mainstream NVM technologies.

2:00

THE 3RD DIMENSION: DESIGN AND SEMICONDUCTOR TECHNOLOGY FOR TOMORROW'S 3D INTEGRATED PRODUCTS
Bart Swinnen, IMEC

3D integration explores the possibilities of interconnecting devices that are in different 2D planes. These 3D-interconnects can play at different levels of the wiring hierarchy, from the package, over the global to the local interconnect levels. 3D interconnect technology enables high transistor density, fast interconnects, integration of heterogeneous technologies and consequently an increase of system functionality. Many 3D integration schemes have been proposed in literature and the different approaches generally can be classified according to the level at which the 3D interconnect breaks into the classical system interconnect hierarchy. Thus, depending on the technology platform that has been used to create it, the 3D interconnect may play at board or package interconnect level, at Back-end global and intermediate interconnect levels, or even at the local interconnect levels.

This short course will review technology features and options for the different classes of 3D technologies. The course will also identify a number of design and technology gaps and opportunities that come about with emerging 3D technologies.

3:00

BREAK

3:30

CHIP PACKAGING TECHNOLOGY
Raj Master, AMD

4:30

HETEROGENEOUS SYSTEM INTEGRATION – TECHNOLOGY FUSION FOR THE COST-EFFECTIVE DESIGN AND MINIATURIZATION OF COMPLEX SYSTEMS
Chris Van Hoof, IMEC

The integration of various electronic and non-electronic functionalities in a very small volume is generally termed heterogeneous integration. The established technological miniaturization approaches have been either SiP or SoC based. However, emerging 2D/3D technologies are causing this distinction to fade, and are starting to enable new complex system applications. This tutorial will highlight key emerging heterogeneous system applications in the RF, medical, MEMS and sensoric field. Particular attention will be given to the expected and/or demonstrated system benefits. In addition, design as well as integration challenges will be discussed.

5:30

ADJOURN