2008 Technical Program

Tuesday, June 3

SESSION 5: MATERIALS AND PROCESSING II
Co-chairs: Co-Chairs: Michael Armacost, Applied Materials and Vincent Arnal, STMicroelectronics

8:00
5.1 INVITED: Post-Etch Cleaning for Porous Low-k Integration: Iimpact of HF Wet Etch on "Pore-Sealing and "k recovery",
L. Broussous, W. Puyrenier, D. Rebiscoul*, V. Rouessac**, and A. Ayral**, STMicroelectronics, Crolles, France, *LETI/CEA, Grenoble, France and **Institut European des Membranes, Montpellier, France

8:25
5.2 INVITED: Progress, Opportunities and Challenges in Modeling of Plasma Etching,
M.J. Kushner, Iowa State University, Ames, IA

8:50
5.3 Enhancing Yield and Reliability by Applying Dry Organic Acid Vapor Cleaning to Copper Contact Via-Bottom for 32-nm Nodes and Beyond,
H. Kudo, K. Ishikawa, M. Nakaishi*, A. Tsukune, S. Ozaki, Y. Nakata, S. Akiyama*, Y. Mizushima, M. Hayashi, A A. Akbar*, T. Kouno, H. Iwata, Y. Iba, T. Ohba**, T. Futatsugi, T. Nakamura, and T. Sugii, Fujitsu Laboratories, Ltd. and *Fujitsu Ltd., Akiruno, Japan and **University of Tokyo, Tokyo, Japan

9:15
5.4 ALD Growth of a Mixed-Phase Novel Barrier for Seedless Copper Electroplating Applications,,
S. Kumar, H.L. Xin*, P. Ercius*, D.A. Muller* and E. Eisenbraun, and The University at Albany-SUNY, Albany, NY and * Cornell University, Ithaca, NY

9:40
5.5 Effects of Ru-Ta Alloy Barrier on Cu Filling and Reliability for Cu Interconnects,
K. Mori, K. Ohmori, N. Torazawa*, S. Hirao*, S. Kaneyama*, H. Korogi*, K. Maekawa, S. Fukui, K. Tomita, M. Inoue, H. Chibahara, Y. Imai, N. Suzumura, K. Asai, and M. Kojima, Renesas Technology Corp., Hyogo, Japan and *Matushita Electric Industrial Co., Ltd., Kyoto, Japan

10:05
BREAK

10:25
5.6 Amorphous Ru / Polycrystalline Ru Highly Reliable Stacked Layer Barrier Technology,
S. Ogawa, N. Tarumi, M. Abe, M. Shiohara, H. Imamura, and S. Kondo, Semiconductor Leading Edge Technologies, Inc., Ibaraki, Japan

9:50
5.7 INVITED: Carbon Nanotubes for use in Electronics?,
W.I. Milne, Cambridge University, Cambridge, UK

SESSION 6: RELIABILITY I
Co-chairs: Co-chairs: Tomoji Nakamura, Fujitisu Labs. and Maureen Brongo, Skyworks Solutions

11:15
6.1 Low-k Dielectric Reliability: Impact of Test Structure Choice, Copper and Integrated Dielectric Quality.
Z. Tokei, IMEC, Leuven, Belgium

11:40
6.2 Blech Effect and Lifetime Projection for Cu/Low-K Interconnects,
C. Christiansen, B. Li and J. Gill*, IBM Systems & Technology Group, Essex Junction, VT and *Hopewell Junction, NY

12:05
6.3 Further Enhancement of Electro-migration Resistance by Combination of Self-aligned Barrier and Copper Wiring Encapsulation Techniques for 32-nm Nodes and Beyond,
H. Kudo, M. Haneda, T. Tabira, M. Sunayama, N. Ohtsuke, N. Shimizu, H. Ochimizu, T. Tsukune, T. Suzuki, H. Kitada, S. Amari*, H. Matsuyama*, T. Owada*, H. Watantani*, T. Futatsugi, T. Nakamura, and T. Sugii, Fujitsu Laboratories, Ltd. and *Fujitsu Ltd., Akiruno, Japan

12:30
LUNCH

SESSION 7: POSTER II
1:15 - 3:00
Exhibit Hall

7.1 Integration Aspects of CoWP Capping Layers for Electromigration Enhancement,
A. Preusse, R. Seidel, O. Aubel, M. Nopper, B. Freudenberg, M. Schaller, M. Fecher, T. Letz, C. Bartsch, A. Ott, M. Friedemann, F. Feustel, M.A./Meyer, and P. Limbecker, AMD, Dresden, Germany

7.2 Investigation of the Impact of CoWP Self-aligned Barrier Deposition on the Porous SiOC Properties after a Direct CMP Process,
S. Gall, S. Olivier, M. Assous, M. Bernard, P.H. Hasumesser, C. Jayet, S. Maitrejean, K. Hamioud*, V. Arnal*, and G. Passemard*, CEA-LETI-MINATEC, Grenoble, France and *STMicroelectronics, Crolles, France

7.3 Reduction of Electrical Crosstalk in Hybrid Backside Illuminated CMOS Imagers using Deep Trench Isolation,
K. Minoglou, K. De Munck, D.S. Texcan, T. Borgers, W. Ruythooren, J. Bogaerts*, I.F. Veltroni** I. Zayer^, R. Meynart^, J-L. Bezy^, C. Van Hoof, and P. De Moor, IMEC, Leuven, Belgium, *CMOSIS, Antwerp, Belgium, **Galileo Avionica, Florence, Italy, and ^ESA-ESTEC, Noordwijk, The Netherlands

7.4 Interconnect for Out-of-Plane MEMS Assembly,
A.A.A. Aarts, H.P. Neves, R.P. Puers*, and C. Van Hoof, IMEC, Leuven, Belgium and *KULeuven, Leuven, Belgium

7.5 Impact of Process Induced Stresses and Chip-Packaging Interaction on Reliability of Air-gap Interconnects,
X. Zhang, S-K. Ryu, R. Huang, P.S. Ho, J. K. Liu*, and D. Toma*, The University of Texas, Austin, TX and *Tokyo Electron US Holdings, Austin, TX

7.6 Measurements and Circuit Model of Carbon Nanofibers at Microwave Frequencies,
R. R. Madriz, J.R. Jameson, S. Krishnan, K. Gleason, Z. Sun, and C.Y. Yang, Santa Clara University, Santa Clara, CA

7.7 Resistivity Size Effect in Encapsulated Cu Thin Films,
T. Sun, B. Yao, A. Warren, V. Kumar*, K. Barmak*, and K.R. Coffee, University of Central Florida, Orlando, FL and *Carnegie Mellon University, Pittsburgh, PA

7.8 Benchmarking of Metal-to-Carbon Nanotube Side Contact Resistance,
Z. Liu, L. Ci, N. Bajwa, Ajayan, and J-Q. Lu, Rensselaer Polytechnic Institute, Troy, NY

7.9 Integration of Low Resistive CVD-W Interconnects for sub-50nm FEOL Application,
C-H. Kim, I-C. Rho, K-B. Rouh, K-Y. Lim, Y-S. Kim, J-C. Ku, Y-S. Sohn, H-S. Kang, and H-J. Kim*, Hynix Semiconductor, Inc., Kyoungki-do, Korea and *Seoul National University, Seoul, Korea

7.10 Investigation of Interconnect Design on Chip Package Interaction and Mechanical Reliability of Cu/Low-k Multi-Layer Interconnects in Flip Chip Package,
C.J. Uchibori, X. Zhang, P.S. Ho*, and T. Nakamura**, Fujitsu Labs., America, Sunnyvale, CA, *University of Texas, Austin, TX and **Fujitsu Labs., Ltd., Kanagawa, Japan

7.11 Realization of Via Interconnects based on Carbon Nanotubes,
J.C. Coiffic, M. Fayolle, H. Le Poche, S. Maitrejean, and S. Olivier, CEA-LETI-MINATEC, Grenoble, France and *CEA-LITEN, Grenoble, France

7.12 Plasma Enhanced Atomic Layer Deposition of Ru-Ta Composite Film as a Seed Layer for CVD Cu Filling,
D. Jeoung, H. Inoue, and H. Shinriki, ASM Japan, Tokyo, Japa

7.13 An Evaluation of Electrografted Copper Seed Layers for Enhanced Metallization of Deep TSV Structures,
S. Ledain, C. Bunel, P. Mangaigalli*, A. Carles*, N .Frederich**, E. Delbos**, L. Omnes**, and A. Etchberry^, NXP Semiconductors, Colombelles, France, *Alchimer S.A., Massy, France, **OM Broup, Saint Fromond, France, and ^University de Versailles, Versailes, France

SESSION 8: RELIABILITY II
Co-Chairs: Scott List, SRC and Shinichi Ogawa, SELETE

3:00
8.1 Copper Line Resistance Control and Reliability Improvement by Surface Nitridation of Ti barrier Metal,
A. Sakata, S. Kato, Y. Yano, H. Toyoda, T. Kawanoue, M. Hatano, J. Wada, N. Yamada, T. Oki, H. Yamaguchi, N. Nakamura, K. Higashi, M. Yamada, T. Fujimake, and M. Hasunuma, Toshiba Corp., Yokohama, Japan

3:25
8.2 TDDB Kinetics and their Relationship with the E- and vE –models,
K-Y. Yiang, H.W. Yao and A. Marathe, Advanced Micro Devices, Inc. Sunnyvale, CA

3:50
8.3 Quantitative Roadmap for Optimizing CMP of Ultra-Low-k Dielectrics,
T-S. Kim, T. Konno*, T. Yamanaka*, and R.H. Dauskardt, Stanford University, Stanford, CA and *JSR Micro, Inc., Sunnyvale, CA

4:15
8.4 Impact of LER and Misaligned Vias on the Electric Field in Nanometer-Scale Wires,
M. Stucchi and Z. Tokei, IMEC, Leuven, Belgium

4:40
8.5 Limitation of Low-k Reliability due to Dielectric Breakdown at Vias,
S.-C. Lee, A.S. Oates and K.M. Chang*, Taiwan Semiconductor Manufacturing Co., Hsinchu, Taiwan, ROC and *National Chiao Tung University, Hsinchu, Taiwan, ROC

5:05
SUPPLIER SEMINARS

© 2007-2008 IEEE all rights reserved. Photo: Bart Edson