2008 Technical Program

Wednesday, June 4

SESSION 9: SYSTEM-ON-CHIP
Co-Chairs: hector Sanchez, Freescale Semiconductor and Gary Ray, Intel Corp.

8:15
9.1 INVITED: Performance Benchmarking for Graphene Nanoribbon, Carbon Nanotube, and Copper Interconnects,
A. Naeemi and J. Meindl, Georgia Institute of Technology, Atlanta, GA

8:40
9.2 Crosstalk Analysis Method of 3-D Solenoid On-chip Inductors for High-speed CMOS SoCs,
K. Hijoka, A .Tanabe, Y. Amamiya, and Y. Hayashi, NEC Corp., Kanagawa, Japan

SESSION 10: PROCESS INTEGRATION I
Co-Chairs: Didier Louis, CEA-LETI and Toshiaki Hasegawa, Sony Corp.

9:05
INVITED: A Multi-level Cu/Low-K/Airgap BEOL Technology,
S. Nitta, IBM T.J. Watson Research Center, Yorktown Heights, NY

9:30
10.2 Cost-effective Air-gap Interconnects by All-in-One Post-Removing Process,
N. Nakamura, N. Matsunaga, T. Kaminatsui, K. Watanabe, and H. Shibata, Toshiba Corp., Yokohama, Japan

9:55
10.3 300 mm Multi Level Air Gap Integration for Edge Interconnect Technologies and Specific High Performance Applications,
R. Gras, F. Gaillard*, D. Bouchu*, A. Farcy, E. Petiprez, B. Icard*, J.C. Le-Denmat, L. Pain*, J. Bustos, P.H. Hausmesser*, P. Brun*, G. Imbert, L. Clement, C. Brorwiak, M. Rivoire, E. Euvrad*, V. Arnal, S. Olivier*, S. Moreau*, M. Mellier, T. Chevolleau**, G. Passemard, and J. Torres, STMicroelectronics, Crolles, France, *CEA-LETI-MINATEC, Grenoble, France and **CNRS-LTM, Grenoble, France

10:20
BREAK

10:30
10.4 Self Aligned CuGeN Process for 32/22nm Nodes and Beyond,
.S. Liu, H.C. Chen, T.I. Bao, J. VanOlmen*, K. Croes*, E. VanBesien*, M. Pantouvaki*, C. Zhao*, E. Sleeckx*, G. Beyer*, and C.H. Yu, Taiwan Semiconductor Manufacturing Co., Hsinchu, Taiwan and *IMEC, Leuven, Belgium

10:55
10.5 Ti-based Barrier for Cu Interconnect Applications,
W. Wu, H-J. Wu, G. Dixit, R. Shaviv, M. Gao, T. Mountsier, G. Harm, A. Dulkin, N. Fuchigami, S.K. Kailasam, E. Klawuhn, and R.H. Havemann, Novellus Systems, Inc., San Jose, CA

11:20
10.6 Highly-Reliable Low-Resistance Cu Interconnects with PVD-Ru/Ti Barrier Metal toward Automotive LSIs,
M. Tagami, N. Furutake, S. Saito, and Y. Hayashi, NEC Corp., Kanagawa, Japan

11:45
10.7 Robust BEOL Process Integration with Ultra Low-k (k=2.0) Dielectric and Self-Formed MnOx Barrier Technology for 32 nm-node and Beyond,
T. Watanabe, Y. Hayashi, H. Tomizawa, T. Usui, A. Gawase, M. Shimada, K. Watanabe, and H. Shibata, Toshiba Corp., Yokohoma, Japan

12:10
LUNCH

SESSION 11: PROCESS INTEGRATION II
Co-Chairs: Shin-Puu Jeng, TSMC and J.D. Luttmer, University of North Texas

1:15
11.1 INVITED: High Volume Manufacturing Issues for On-Die Interconnects at the 45nm Process Node,
P. Moon, Intel LTD (Logic Technology Development) Hillsboro, Oregon

1:40
11.2 Low-K Interconnect Stack with Thick Metal 9 Redistribution Layer and Cu Die Bump for 45nm High Volume Manufacturing,
D. Ingerly, S. Agraharam, D. Becher, V. Chikarmane, K. Fischer, R. Grover, M. Goodner, S. Haight, J. He, T. Ibrahim, S. Joshi, H. Kotheri, K. Lee, Y. Lin, C. Litteken, H. Liu, E. Mays, P. Moon, T. Mule, S. Nolen, N. Patel, S. Pradhan, J. Robinson, P. Ramanarayanan, S. Sattiraju, T. Schroeder, S. Williams, and P. Yashar, Intel Corp., Hillsboro, OR

2:05
11.3 INVITED: Phase Change Memory
M. Breitwisch, IBM, Essex Junction, VT

2:30
11.4 Quantitative Analysis of Correlation between Insulator Surface Copper Contamination and TDDB Lifetime based on Actual Measurement,
D. Oshida, T. Takewaki, M. Iguchi, T. Taiji, T. Morita, Y. Tsuchiya, H. Tsuchiya, S. Yokogawa, H. Kunishima, H. Aizawa, and N. Okada, NEC Electronics Corp., Kanagawa, Japan

2:55
11.5 Low-Temperature Plasma-Oxidation Process for Reliable Tantalum-Oxide (TaO) Decoupling Capacitors,
I. Kume, N. Inoue, T. Toda*, M. Furumiya*, T. Takeuchi, F. Ito, T. Iwaki*, S. Shida*, and Y. Hayashi, NEC Corp. and *NEC Electronics, Kanagawa, Japan

3:20
BREAK

SESSION 12: NOVEL MATERIALS AND PROCESSES
Co-Chairs: Dorel Toma, Tokyo Electron US Holdings and Johann Bartha, Technical University Dresden

3:30
12.1 INVITED: Germanium on Silicon Modulators and Nanometallic-Enhanced Detectors for Optical Interconnects
D.A.B. Miller, Stanford University, Stanford, CA

3:55
12.2 Sub-ns Delay Through Multi-Wall Carbon Nanotube Local Interconnects in a CMOS Integrated Circuit
G.F. Close, S. Yasuda*, B. Paul**, S. Fujita*, and H-S. P. Wong, Stanford, CA, *Toshiba Corp., Kawasaki, Japan and **Toshiba America Research, San Jose, C

4:20
12.3 Robustness of CNT Via Interconnect Fabricated by Low Temperature Process over a High-Density Current
A. Kawabata, S. Sato, T. Nozue, T. Huakshima, M. Norimatsu, M. Mishima, T. Murakama, D. Kondo, K. Asano, M. Ohfuti, H. Kawarada*, T. Sakai, M. Nihei, and Y. Awano, MIRAI-Selete, Atsugi, Japan and *Waseda University, Tokyo, Japan

4:45
CONFERENCE ENDS

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